| Message ID | 20240607095754.265105-10-christophe.roullier@foss.st.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Series to deliver Ethernet for STM32MP13 | expand |
On 6/7/24 11:57 AM, Christophe Roullier wrote: [...] > @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { > status = "disabled"; > }; > > + ethernet1: ethernet@5800a000 { > + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; > + reg = <0x5800a000 0x2000>; > + reg-names = "stmmaceth"; > + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, > + <&exti 68 1>; > + interrupt-names = "macirq", "eth_wake_irq"; > + clock-names = "stmmaceth", > + "mac-clk-tx", > + "mac-clk-rx", > + "ethstp", > + "eth-ck"; > + clocks = <&rcc ETH1MAC>, > + <&rcc ETH1TX>, > + <&rcc ETH1RX>, > + <&rcc ETH1STP>, > + <&rcc ETH1CK_K>; > + st,syscon = <&syscfg 0x4 0xff0000>; > + snps,mixed-burst; > + snps,pbl = <2>; > + snps,axi-config = <&stmmac_axi_config_1>; > + snps,tso; > + access-controllers = <&etzpc 48>; Keep the list sorted.
On 6/7/24 14:48, Marek Vasut wrote: > On 6/7/24 11:57 AM, Christophe Roullier wrote: > > [...] > >> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { >> status = "disabled"; >> }; >> + ethernet1: ethernet@5800a000 { >> + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; >> + reg = <0x5800a000 0x2000>; >> + reg-names = "stmmaceth"; >> + interrupts-extended = <&intc GIC_SPI 62 >> IRQ_TYPE_LEVEL_HIGH>, >> + <&exti 68 1>; >> + interrupt-names = "macirq", "eth_wake_irq"; >> + clock-names = "stmmaceth", >> + "mac-clk-tx", >> + "mac-clk-rx", >> + "ethstp", >> + "eth-ck"; >> + clocks = <&rcc ETH1MAC>, >> + <&rcc ETH1TX>, >> + <&rcc ETH1RX>, >> + <&rcc ETH1STP>, >> + <&rcc ETH1CK_K>; >> + st,syscon = <&syscfg 0x4 0xff0000>; >> + snps,mixed-burst; >> + snps,pbl = <2>; >> + snps,axi-config = <&stmmac_axi_config_1>; >> + snps,tso; >> + access-controllers = <&etzpc 48>; > > Keep the list sorted. Hi Marek, As already explained, all MP13 IPs have this property before "status". If we must move this property, we will do it later and do it for all IPs. Thanks
Hi Marek On 6/7/24 14:48, Marek Vasut wrote: > On 6/7/24 11:57 AM, Christophe Roullier wrote: > > [...] > >> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { >> status = "disabled"; >> }; no space here ? >> + ethernet1: ethernet@5800a000 { >> + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; >> + reg = <0x5800a000 0x2000>; >> + reg-names = "stmmaceth"; >> + interrupts-extended = <&intc GIC_SPI 62 >> IRQ_TYPE_LEVEL_HIGH>, >> + <&exti 68 1>; >> + interrupt-names = "macirq", "eth_wake_irq"; >> + clock-names = "stmmaceth", >> + "mac-clk-tx", >> + "mac-clk-rx", >> + "ethstp", >> + "eth-ck"; >> + clocks = <&rcc ETH1MAC>, >> + <&rcc ETH1TX>, >> + <&rcc ETH1RX>, >> + <&rcc ETH1STP>, >> + <&rcc ETH1CK_K>; >> + st,syscon = <&syscfg 0x4 0xff0000>; >> + snps,mixed-burst; >> + snps,pbl = <2>; >> + snps,axi-config = <&stmmac_axi_config_1>; >> + snps,tso; >> + access-controllers = <&etzpc 48>; > > Keep the list sorted. The list is currently not sorted. I agree that it is better to have a common rule to easy the read but it should be applied to all the nodes for the whole STM32 family. Maybe to address by another series. For the time being we can keep it as it is. Alex
On 6/10/24 10:06 AM, Alexandre TORGUE wrote: > Hi Marek Hi, > On 6/7/24 14:48, Marek Vasut wrote: >> On 6/7/24 11:57 AM, Christophe Roullier wrote: >> >> [...] >> >>> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { >>> status = "disabled"; >>> }; > no space here ? >>> + ethernet1: ethernet@5800a000 { >>> + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; >>> + reg = <0x5800a000 0x2000>; >>> + reg-names = "stmmaceth"; >>> + interrupts-extended = <&intc GIC_SPI 62 >>> IRQ_TYPE_LEVEL_HIGH>, >>> + <&exti 68 1>; >>> + interrupt-names = "macirq", "eth_wake_irq"; >>> + clock-names = "stmmaceth", >>> + "mac-clk-tx", >>> + "mac-clk-rx", >>> + "ethstp", >>> + "eth-ck"; >>> + clocks = <&rcc ETH1MAC>, >>> + <&rcc ETH1TX>, >>> + <&rcc ETH1RX>, >>> + <&rcc ETH1STP>, >>> + <&rcc ETH1CK_K>; >>> + st,syscon = <&syscfg 0x4 0xff0000>; >>> + snps,mixed-burst; >>> + snps,pbl = <2>; >>> + snps,axi-config = <&stmmac_axi_config_1>; >>> + snps,tso; >>> + access-controllers = <&etzpc 48>; >> >> Keep the list sorted. > > The list is currently not sorted. I agree that it is better to have a > common rule to easy the read but it should be applied to all the nodes > for the whole STM32 family. Maybe to address by another series. For the > time being we can keep it as it is. Why is the st,... and snps,... swapped anyway ? That can be fixed right here. Why is the access-controllers at the end ? That can be fixed in separate series, since that seems to have proliferated considerably.
On 6/10/24 12:37, Marek Vasut wrote: > On 6/10/24 10:06 AM, Alexandre TORGUE wrote: >> Hi Marek > > Hi, > >> On 6/7/24 14:48, Marek Vasut wrote: >>> On 6/7/24 11:57 AM, Christophe Roullier wrote: >>> >>> [...] >>> >>>> @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { >>>> status = "disabled"; >>>> }; >> no space here ? >>>> + ethernet1: ethernet@5800a000 { >>>> + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; >>>> + reg = <0x5800a000 0x2000>; >>>> + reg-names = "stmmaceth"; >>>> + interrupts-extended = <&intc GIC_SPI 62 >>>> IRQ_TYPE_LEVEL_HIGH>, >>>> + <&exti 68 1>; >>>> + interrupt-names = "macirq", "eth_wake_irq"; >>>> + clock-names = "stmmaceth", >>>> + "mac-clk-tx", >>>> + "mac-clk-rx", >>>> + "ethstp", >>>> + "eth-ck"; >>>> + clocks = <&rcc ETH1MAC>, >>>> + <&rcc ETH1TX>, >>>> + <&rcc ETH1RX>, >>>> + <&rcc ETH1STP>, >>>> + <&rcc ETH1CK_K>; >>>> + st,syscon = <&syscfg 0x4 0xff0000>; >>>> + snps,mixed-burst; >>>> + snps,pbl = <2>; >>>> + snps,axi-config = <&stmmac_axi_config_1>; >>>> + snps,tso; >>>> + access-controllers = <&etzpc 48>; >>> >>> Keep the list sorted. >> >> The list is currently not sorted. I agree that it is better to have a >> common rule to easy the read but it should be applied to all the nodes >> for the whole STM32 family. Maybe to address by another series. For >> the time being we can keep it as it is. > > Why is the st,... and snps,... swapped anyway ? That can be fixed right > here. I agree. > > Why is the access-controllers at the end ? That can be fixed in separate > series, since that seems to have proliferated considerably. Yes for all other nodes using this bus firewall binding but in a separate series
diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6704ceef284d3..e1a764d269d27 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -979,6 +979,12 @@ ts_cal1: calib@5c { ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; etzpc: bus@5c007000 { @@ -1505,6 +1511,38 @@ sdmmc2: mmc@58007000 { status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + access-controllers = <&etzpc 48>; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 3e394c8e58b92..73e470019ce42 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -68,4 +68,35 @@ channel@18 { }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + access-controllers = <&etzpc 49>; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; };
Both instances ethernet based on GMAC SNPS IP on stm32mp13. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com> --- arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++ 2 files changed, 69 insertions(+)