From patchwork Tue Jun 11 13:01:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 13693735 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9198717D35F; Tue, 11 Jun 2024 13:03:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718111038; cv=none; b=F+GEYFpEGiGc2Ts6cS6HkKcBaoa69Q56jIwH7M26G5zSg5xiXaKSrFQyVxuvRHuvBRkDhaI4CizrSfMsCg0o5CaI7k/Zgm1whAo6xXas2PbFMH850SGh0BlQxQIpwyINv5980wtzoFyFn5XQEEQz64pab7SOeQX0nPGYm8/vN4k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718111038; c=relaxed/simple; bh=4Ply91MrZiEzYEMlYcEjcsPFLaA7oPbDhDkBP1ulJQk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kVfJVz5Gc0ZUMXCB72na1CQWKiZw+E3Nfbw5BdcqPaIsc0RIPaUWE3kG0U9068SxzzAi9o3XItBW+nqJ9r3/NQD0weuQ9bX0yDe/8Sb2dhLIS1jFiPILVfA8Na3w0HVJAGyzkXQHJWnLg9GulEzP3DIWH5zPQWyDpoGG/Uaddbc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=h6Cm9G+c; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="h6Cm9G+c" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 45BBluxp017717; Tue, 11 Jun 2024 15:03:15 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= jWA+Y98zKo81ks8axrj4D4lZ6qT5+GF1eFXzK0OUGtc=; b=h6Cm9G+cnUggZJrv E6DOe0pwZHiBzYcseb750mWFdtlaIkDtbKxjgxTp9Q8S803TsbzX0F7tNO7Fn2dy iRrQaPA2u6MDTbBBn7bsgxu0yl90q/HijgiL0O3ee1Gp21hP0WJJgvDuRQNtHggK yTgmSHnvtSH+mbyCQvT8a51tIybNORs9p87GH5PPBksSh5e1s/C8r1i3hkUWb9CA vJhWWl0Hh/3TTjSSKb7f97kw0SlDQdFgWgGTFgKBGPpwQpXD6EUbLv2ZqcLvq6qr gg5sWAUFjsSpxmAh4sv2ym+9FjRZBCQ/ykFOHQUqXaxTs1oNnYn5r1o4rSZBl4/B NZXWww== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3ypbp2k2nq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 11 Jun 2024 15:03:15 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5015F4005C; Tue, 11 Jun 2024 15:03:10 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2603C214D31; Tue, 11 Jun 2024 15:01:58 +0200 (CEST) Received: from localhost (10.48.86.164) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 11 Jun 2024 15:01:57 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier , Marek Vasut CC: , , , , Subject: [PATCH v2 2/3] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Date: Tue, 11 Jun 2024 15:01:09 +0200 Message-ID: <20240611130110.841591-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240611130110.841591-1-christophe.roullier@foss.st.com> References: <20240611130110.841591-1-christophe.roullier@foss.st.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-06-11_07,2024-06-11_01,2024-05-17_01 Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier Reviewed-by: Marek Vasut --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 32c5d8a1e06ac..7f72c62da0a64 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,77 @@ pins { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */