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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 1/6] net/mlx5: Correct TASR typo into TSAR Date: Fri, 14 Jun 2024 00:00:31 +0300 Message-ID: <20240613210036.1125203-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240613210036.1125203-1-tariqt@nvidia.com> References: <20240613210036.1125203-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4C:EE_|SJ1PR12MB6051:EE_ X-MS-Office365-Filtering-Correlation-Id: 16b81fb7-9464-4ee4-be8e-08dc8bec19c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230035|376009|82310400021|1800799019|36860700008; X-Microsoft-Antispam-Message-Info: wy/wzhBWafKDYrntu04ZQXoRVBXaf8Hg/FNJjE0+lyfv2GJfiba5+UHHfd3LnyZx6k8jGXZWVtcNtIQHAh3qDmikI90CC8HHPfgClc8Uhz1Wz9bLuetRI43/OC30WyzgC7btHKARbynPrcrGw0EBTBfi054V2xRMGLcWMrBzB1MRpuBzTGK9TF0He5iGzIb+dFHd+syKprOrI8BOqnSdOWpsJqj9w8sEG2v/C9wTpiEjF/UdlAc32E9Zc7TXRLluRtuec9wQzmcc6KRbtRR2mPpzScBfAOj5bN1uVmEr0c7TtvTw9pXtggr1IrGIXnAcM/BSJuGaN/XJcqpiAOgY3ez43Gxeq966/5SHd93kwlxtgCgiWAcIRGGT4smF2rJbvFYhL4l2XAA2F+baVJLmpEtcGHDkL5fYlKj6Yu6w95K0D6cZVELAkCbdA7cAZ2pbbCZQy8PhGVkzNKrdgJp90aHrK36zC82N7EgF2iSAX6+WdcdLLlQssC9KDutsclqs7GuB7KA0Ubw8InnrF0q3MGreeWaLBHm0+J7V9mFTf/xwMtNppphM5t0JVaY/DmWuvjEaS+U/Kxd8vfr7Y2VaCQxg9icGvjkXM7jR9ki2qbZgoHAxOtWskzYfxnHOWR0P4PgExcRfeXMDAd+VZ4OJX1NA4EOuit0pbHOmDXmPuwsx2Y9qIITN/LOv/z8O9W5bnuJDab7DtbhMx7f4gCq3Rx7GZWOOVfYljJS/EwxQG38oJJA3FkaC3xYu32ry+RdZiPT2gQZV8Uq2iYLcO5cen2J1CkEOutrWCVsr+dhKozgF18FaSoYTkint1N1jygqX1vYrzc1IixwzMmi6TLLwULi+NcYBekq3wWOwJ1Sd6tgImZFUIw18eQzYe2OdIpLSnmTpcepVxg1Dp6V26pK/CyMiGp7SXpgzLoWHQM57Y/hgo3ha7z4Wu1VurbZWRfSN+mDBUXPpje0GERsXSdzGoJ4tVZ/JTxPMjdHSb9oEbO+qsuMIVoPgTcbpDQwX36Uca61wEt1DJDGOKg9Npb/rI86TvwMF7zF2t3eKt/nwoaaTSt1yACwu7+KCPnqpG7FiVs6vU1o6lLCqbsQfV2E/0sVYcF9ERHEnn/lTwFRXLUhkzzRexw3IRZ33qvNetGIsWAb5kxrQ3q/Hy1dbNIAqnDE1EY7rFmDufVcZuCElLfB+1wOWWKeFyCNwNmZOsVsr+RiuKpleJo5OrEPjmcbOLWcshQYaZrL5lFPC4Tk4C0xxtA2q2c7zoZXEsj1M5f13a7x3C/mFn48iyV9z/Vxvrb8l8Go67K6+es7yr79rozT32WudBjlXw61VMhp/sulMU0MkHnapgijWcTc9XrRkWaAkoTkJkyabinDt8zhfnFm/37qdqHEBaKbVa3PZUCeb3EiloEOeHtGriEdDqoBRFQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230035)(376009)(82310400021)(1800799019)(36860700008);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jun 2024 21:02:13.8578 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 16b81fb7-9464-4ee4-be8e-08dc8bec19c6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6051 X-Patchwork-Delegate: kuba@kernel.org From: Cosmin Ratiu TSAR is the correct spelling (Transmit Scheduling ARbiter). Signed-off-by: Cosmin Ratiu Reviewed-by: Gal Pressman Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 2 +- include/linux/mlx5/mlx5_ifc.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index d2ebe56c3977..20146a2dc7f4 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -531,7 +531,7 @@ static bool esw_qos_element_type_supported(struct mlx5_core_dev *dev, int type) switch (type) { case SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR: return MLX5_CAP_QOS(dev, esw_element_type) & - ELEMENT_TYPE_CAP_MASK_TASR; + ELEMENT_TYPE_CAP_MASK_TSAR; case SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT: return MLX5_CAP_QOS(dev, esw_element_type) & ELEMENT_TYPE_CAP_MASK_VPORT; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 17acd0f3ca8e..466dcda40bb5 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -3914,7 +3914,7 @@ enum { }; enum { - ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, + ELEMENT_TYPE_CAP_MASK_TSAR = 1 << 0, ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,