From patchwork Mon Jun 17 20:16:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13701370 Received: from EUR03-VI1-obe.outbound.protection.outlook.com (mail-vi1eur03on2086.outbound.protection.outlook.com [40.107.103.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AB231990D2; Mon, 17 Jun 2024 20:17:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.103.86 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718655466; cv=fail; b=tXbni97eQGsOVd9XaUfGq9Eg4sogZkC/QB4jlG8rZ4kv22ieQJ8QUnup7BKqD3SyPDqsMorxR8Pa4G3UZRS784EEU6fgV1IY8sqOP/zU+qZ0ms1QSdLh/5oR5sgtMXfbTNj63S+zSeWHU4eYpG9f31YnSRzIY6Cy6aGilJghPOA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718655466; c=relaxed/simple; bh=EnlJL+A6hrb+lx0OJcd5b43KT+ZkB7ImYpV0nsydYlM=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=KpF+D/m4ejZuc5g6GUIt7HbKHBsVg4x/ID9V3djxIwsfCqTBrpGDeOe6cd0YPTqBapReTkrD61BtK6zGPuKghKKL/5ulDRlGgjscqECUqaJRjh8ty8EvtasllhQOGxNuIFtlsngJ9b9BoNuU7pTXvX3micXMEvQLQjKFWMgZ+aw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b=e9tRNIIr; arc=fail smtp.client-ip=40.107.103.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=nxp.com header.i=@nxp.com header.b="e9tRNIIr" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=X8/Wh2ZXYHLbV0dFC3EWXP0D4Zq5zlKHP1PMzAnsLm68kzDYQ3xzmj5r+8Dpt+843a6qMcBDzj5nIZBZGxSg7Og3YMk3SSobtAgc7PbJ3TaulBn7cENaKx6IVq3HY7Y92fZxDZqKX0mXxaIVdIdwwSAqGevpfPiRD9HbVfcEXRcVJPMZSU2JEeoG8Op6F7pGe8LDnqY1EzjNbJ8A9LFFl/O4BFyhQPJmJ/0t5icsDQi+Evqg0SJug03RPMSvxFagnJsNzy4vLqkhaiZj1ZU3Ea3+kconEmKl9l2gQWP0Ug5iFt+VPI527gWp3DfcHENuZWcdlcF/GAYqCO8OIdDLjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=8F78DgbEfTJ1B0b5oIHR7efzIOfShRafZmsPxBTuawY=; b=GI4phL2AFzqJZxmOMl2GwxoHTgn8YAw688zPBjPpWRNzloHLkmgwXoCDWg1/KGbFH9iGVDGvCNkc+Z3O8SJkOfFPpgcHpfvl6JElZEWn445xkvkqqG6f6eGKHjAiqODjayczT600SY51tSu3rZi9V3Q8gr8i5dKJ+VAg26ib79k2rShni9xtwCbd3htYYPdPSpvWNsmchgAYlrL0Q//IfWmHz0rmNVsS6vugCUDYp2nBH2aKfm2QNB5V+0znoh+VoslRZSV4rKS4ku3Br+J/mfnSklAdcbvP0TsMGuEzH2vwDBkMMSTQgCmHBMDxlYAApn1BxTT9UTuOF5eu9QeJmg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=8F78DgbEfTJ1B0b5oIHR7efzIOfShRafZmsPxBTuawY=; b=e9tRNIIr1ff5rzgMZCfGG6tfuMqJ1cY8/OfFkWKc4xUqvR6M/i2YKCKefARpajFz8hbe8/R0vKT92gGW1rguiRgv+Z2jEnY3EXymXNGcI5wAmLkjt+h1Ijb8dpccGKwctTyga0c0L4SUkmxdSQWJFPBkKqROiKQ9oxGj8BWDY7g= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by PA4PR04MB7997.eurprd04.prod.outlook.com (2603:10a6:102:c9::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.30; Mon, 17 Jun 2024 20:17:41 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%2]) with mapi id 15.20.7677.030; Mon, 17 Jun 2024 20:17:41 +0000 From: Frank Li Date: Mon, 17 Jun 2024 16:16:41 -0400 Subject: [PATCH v6 05/10] PCI: imx6: Simplify switch-case logic by involve core_reset callback Message-Id: <20240617-pci2_upstream-v6-5-e0821238f997@nxp.com> References: <20240617-pci2_upstream-v6-0-e0821238f997@nxp.com> In-Reply-To: <20240617-pci2_upstream-v6-0-e0821238f997@nxp.com> To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Rob Herring , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Philipp Zabel , Liam Girdwood , Mark Brown , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, bpf@vger.kernel.org, devicetree@vger.kernel.org, Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1718655424; l=7027; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=EnlJL+A6hrb+lx0OJcd5b43KT+ZkB7ImYpV0nsydYlM=; b=OIGoZ1KHbNuE5OAwVBmOpVWgR0A2KiKP+p0JiLEqdLDRZoDret84ABeKWUG2I1IXMzA9Easrb nnz1ipl1SoSCrueVn4dEvUVGEp1TtMN7C8SLzRxTcZ+oL3MxpZHDKXA X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: SJ0PR05CA0116.namprd05.prod.outlook.com (2603:10b6:a03:334::31) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|PA4PR04MB7997:EE_ X-MS-Office365-Filtering-Correlation-Id: 3af9abbb-5e44-48e2-235b-08dc8f0a8a3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|7416011|1800799021|366013|52116011|38350700011|921017; X-Microsoft-Antispam-Message-Info: =?utf-8?q?N8wMkaZmRQtmYqDjOtmFVopVFLsuLCV?= =?utf-8?q?/4tvPLr0Vr/gv6qSHuAUWfKNxJxuPWU6nDmBWWVzh1p85qC0tmazijV4EIvfuruWI?= =?utf-8?q?QYkAFYuhx7eVkF/NLmCt3HDYd6OzGl/wlvpud+XMuJ9KqYuaia/4zsFK49TQLvy9s?= =?utf-8?q?ElsIXt2/mDuF7LIOQppaZ5fGY9mhnKjmSKcnWGT/RojODKizhOrFrGdGwg41ihmOK?= =?utf-8?q?gNRhsErPHxvYyLvZ0n5yBi6QiZdj3t5glq94mKlp+WNDY1VDxYNbdDVu02Iak//o7?= =?utf-8?q?/7gyNX256pZ2F4O0fkhvLSY6baRu3B4m+iuAxNQ/Jol5KtMZ2HpRxJ01ykN9YXfJe?= =?utf-8?q?H0tpyArXItdFZdpDOkfAIJOcDZxb3juGX6zVEwb6skYXVLpoVFMnVk/xwY+4SLRkN?= =?utf-8?q?yHZMB4QaX0QTJnvAeMpeeE2767+dWH6hxJnoC6a5ak6hjwj8j1n134CHewf9cMCWj?= =?utf-8?q?4p78GwZFiMGwPsf0gCw94td5YaPAKNUXnJfYJoZhfJ/er2RksPfUBIEYX9A+6w3c7?= =?utf-8?q?KM5RrAGWAzzxhVFn6lzoezxo85+MEHSaI7pWg+2x2Xrh3KIYEy2UC9v1VbNxjnrsT?= =?utf-8?q?yenCzgJLpyVj5YEBDCoR6KsGYHH2REfmRk5EE6AtpOHwAHDGqMBwSta3X1euFvZQ6?= =?utf-8?q?hh8qlnISFjSVJxF2OwvUOaa3phL7GGmIkGQ+44t2X6kQMAd6GiBUXdZabSZti6Isj?= =?utf-8?q?pPTxQYoypKOktapXBWXkGzcYnKbwiTgN1nR2fVjaaVBkjZywP2dg13VKLsFedfNnN?= =?utf-8?q?pKH2sfvUbUrpLRlOJJFImt8fubutqNG7ZRlN+myYtaeorGZ5wTfIcP7xdA3va2+gB?= =?utf-8?q?QjOBeFuti5atxGVYU7AvzaC0VQ4bo/xYpIHA2Lyas72GNlRtTo5jUlh9mSl28hne/?= =?utf-8?q?cprBO9brkkZKP1APi9a1Nf+Tm4urS1d8J/IyLFFrGBW6NCubdQTRsKXxRZ4Uj3MRy?= =?utf-8?q?ekfEW+DBTsoxGYjxKuBr8zihWvKJfrf8xSpoJ2+BAtpGxmFYH/7ew5QjvQMW5FEmo?= =?utf-8?q?NVgIiPBNS5JQzgoY1zjSbak/gU+m1hoWcwIu9BrL1F6l3JMA0AWZ8+LGtNZVYC7/E?= =?utf-8?q?zT5EvWRGITsknDrfUuYyZ4kQlu8PjSEhZDeRFxQ02U4PzChESlDVC31ha8iojNfWu?= =?utf-8?q?d8/vgMZFK8MQp/1DPs8Wn5ut+cX9DndB65u+P3M76hUFAB6TMlCizqWqWow6L6EMs?= =?utf-8?q?Y+0c+kdyc2qLq63M0GNXW1ZlaQeP6LFJb5si1BTJOnAR0n3qKgkjAy4ERt/tRdOdZ?= =?utf-8?q?BjKqcH2eb3Q3HRc3X8pAoC+o7mf6w+2/q3GBLnM6Jk4SWvUOHScdxgrDikyk8CuBX?= =?utf-8?q?DoSKgNi/x0EW?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230037)(376011)(7416011)(1800799021)(366013)(52116011)(38350700011)(921017);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?lYt9Hg54SPrc3oD6tg2LDZBNcWQh?= =?utf-8?q?jcHBHebMMHhZnoCab1BpBlKMKKG2QrHJjuLm3gQm+iSMz8vZ9dOV7IqR7183AtDAc?= =?utf-8?q?m/6mCRQvsZd1LECBxv/2nOeeoKC1DtesQlr/fNr0TRXAxKSEESxanAS7SBUX71NsL?= =?utf-8?q?1By1xQU0rf6ycYaLGhFyZYOjxt5cHOuuWBwjQWFGKqeNWjUd1VuVTOJ68NC/oqiWk?= =?utf-8?q?qMgO8+3Ua7yZYWO3RiBeY+BvFvZ8UYSQVvUUELgGD43Vi8eal7+0iVb7d9pFD/oTm?= =?utf-8?q?v85ZlHr8jJPNr/yOOOJ7Epj1QaiSuughrlvt6yvXK0w1A7jDbQCjl6itd5dfIjnAH?= =?utf-8?q?66zMUClqt/40RImebsu53Lz7YhIiznUGrVf8l5ljbrUobOwPp8AyQao87pyIjtr2s?= =?utf-8?q?X4AVH2EvclwKlN5Qclm8JDYnxY4ZSZ5scBsC8hlvroBKZZHK8oSVrA/dpGbRxiYLp?= =?utf-8?q?+eeA/978S80U/kiuTMlxXIYK+jRrDEkzC1+tkJrHCnrUVhovaxa31KNi1Am+qBDhb?= =?utf-8?q?tHzXRRxWPLPqnq5Y2lZu8F0cDzgrYuxSb15cd8Z7PosoDKKApSkRcsvP6YrHi0sFf?= =?utf-8?q?ztlnUEnfEWeLPYjT8Vr2aX0gGGuDiHdW9OGgR9+p2kYz5rc4ziYyanwnjjwM8u/Dy?= =?utf-8?q?A34ADgZXL0L/hYQtFdUOCQy3JV9olf8zQpocOwQYhNdmQhj/Ik7pBSED0VxeF7MxW?= =?utf-8?q?daXI4QDAN9nW9Y/NaT6ixGI4ttxql11/8cncvrFBgs9lp4h99KROzQUderEqFZ2nP?= =?utf-8?q?1FZjAIUbd6uzlL7QT/XoYYHozUnblZIOzEd7MMUioLHSrwTKurx61vN9ddg6Lz81Z?= =?utf-8?q?2wntx4Khh6ciB3cJhqglgLoVrk66/TBonyf8VMAeowBdGGz4boOe/k9unB9L7xVl+?= =?utf-8?q?B2Z7Knd0quDsE8W/kfqs4tygKKK87MDYdTkEp4Yg/U1E1GZLVEp7THipVfq+YBYvT?= =?utf-8?q?lNOyGXWtdFQtut8fEB4g+KvTlHtkpDnGySB66VAHDNxQymfzqokWV/zQVPEn8WJEF?= =?utf-8?q?ZY2w8vkuOCG1+p+faVt4a5euatFz8ucKnhQGqIp4d/uCWaPTWhyP7yC4Tw+inD3Hb?= =?utf-8?q?Nl4aAsV47KhCtkueUL7F0aYf1+JSnNtZN+u6D+IQnepm2XO9nx2jsLpiV3BqJhMOs?= =?utf-8?q?PSgqMRB9qVBNOiKEocPb1IiDDbw9XfDlknpm9jnhEoT0pim5aWL1qXF34/3YtbSgy?= =?utf-8?q?lwJckR+UQmB1NfEtKBmw6vv7iTFuoAn0ogJyhlJMaqZ67rd0ks/34K4blumVxb3rN?= =?utf-8?q?fjy6GUaPnfMysIrgcozc1dfkeyXwzMKUgXJYUYkjAk14XS4uzWAD7gjrPc3UcIWNc?= =?utf-8?q?rOT3YT/JSbqcU9vXcova1wnWcY3i4W1HI/7JbCfE4naooR/AfkDbCvZwBtiViiT+7?= =?utf-8?q?AQdTN6kOH07c/i/k8IvgyRcS5tTJPeaPXsUhZtn1FUo0vdpYaaotHswzWICmdhSCP?= =?utf-8?q?65m9sswmdIgFyWqhOZZ4RVY+bRIWBC6xi306s9QkLrFUzng6p5DU3N54kRoWVzLXI?= =?utf-8?q?Xr7TnfMpqZs4?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3af9abbb-5e44-48e2-235b-08dc8f0a8a3b X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 20:17:41.2181 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8CfpRoPxVAkkUWBdhiEqwl/wwg7IkObC7fM2SQ3YPNaHYkmaox5pxOqzTLxUs3YwS/+cT6TYlLFtxsJmE8biUQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB7997 Instead of using the switch case statement to assert/dassert the core reset handled by this driver itself, let's introduce a new callback core_reset() and define it for platforms that require it. This simplifies the code. Signed-off-by: Frank Li Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pci-imx6.c | 134 ++++++++++++++++++---------------- 1 file changed, 71 insertions(+), 63 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index ff9d0098294fa..6f68bee111029 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -104,6 +104,7 @@ struct imx_pcie_drvdata { const struct pci_epc_features *epc_features; int (*init_phy)(struct imx_pcie *pcie); int (*set_ref_clk)(struct imx_pcie *pcie, bool enable); + int (*core_reset)(struct imx_pcie *pcie, bool assert); }; struct imx_pcie { @@ -672,35 +673,75 @@ static void imx_pcie_clk_disable(struct imx_pcie *imx_pcie) clk_bulk_disable_unprepare(imx_pcie->drvdata->clks_cnt, imx_pcie->clks); } +static int imx6sx_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + if (assert) + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, + IMX6SX_GPR12_PCIE_TEST_POWERDOWN); + + /* Force PCIe PHY reset */ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, + assert ? IMX6SX_GPR5_PCIE_BTNRST_RESET : 0); + return 0; +} + +static int imx6qp_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, + assert ? IMX6Q_GPR1_PCIE_SW_RST : 0); + if (!assert) + usleep_range(200, 500); + + return 0; +} + +static int imx6q_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + if (!assert) + return 0; + + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); + regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); + + return 0; +} + +static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + + if (assert) + return 0; + + /* + * Workaround for ERR010728, failure of PCI-e PLL VCO to + * oscillate, especially when cold. This turns off "Duty-cycle + * Corrector" and other mysterious undocumented things. + */ + + if (likely(imx_pcie->phy_base)) { + /* De-assert DCC_FB_EN */ + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); + /* Assert RX_EQS and RX_EQS_SEL */ + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL | PCIE_PHY_CMN_REG24_RX_EQ, + imx_pcie->phy_base + PCIE_PHY_CMN_REG24); + /* Assert ATT_MODE */ + writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); + } else { + dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); + } + imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); + return 0; +} + static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) { reset_control_assert(imx_pcie->pciephy_reset); reset_control_assert(imx_pcie->apps_reset); - switch (imx_pcie->drvdata->variant) { - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN, - IMX6SX_GPR12_PCIE_TEST_POWERDOWN); - /* Force PCIe PHY reset */ - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, - IMX6SX_GPR5_PCIE_BTNRST_RESET); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, - IMX6Q_GPR1_PCIE_SW_RST); - break; - case IMX6Q: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, true); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) @@ -710,47 +751,10 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) { - struct dw_pcie *pci = imx_pcie->pci; - struct device *dev = pci->dev; - reset_control_deassert(imx_pcie->pciephy_reset); - switch (imx_pcie->drvdata->variant) { - case IMX7D: - /* Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. - */ - if (likely(imx_pcie->phy_base)) { - /* De-assert DCC_FB_EN */ - writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, - imx_pcie->phy_base + PCIE_PHY_CMN_REG4); - /* Assert RX_EQS and RX_EQS_SEL */ - writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL - | PCIE_PHY_CMN_REG24_RX_EQ, - imx_pcie->phy_base + PCIE_PHY_CMN_REG24); - /* Assert ATT_MODE */ - writel(PCIE_PHY_CMN_REG26_ATT_MODE, - imx_pcie->phy_base + PCIE_PHY_CMN_REG26); - } else { - dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); - } - - imx7d_pcie_wait_for_phy_pll_lock(imx_pcie); - break; - case IMX6SX: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, - IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); - break; - case IMX6QP: - regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_SW_RST, 0); - - usleep_range(200, 500); - break; - default: - break; - } + if (imx_pcie->drvdata->core_reset) + imx_pcie->drvdata->core_reset(imx_pcie, false); /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx_pcie->reset_gpio)) { @@ -1458,6 +1462,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6q_pcie_core_reset, }, [IMX6SX] = { .variant = IMX6SX, @@ -1473,6 +1478,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx6sx_pcie_init_phy, .set_ref_clk = imx6sx_pcie_set_ref_clk, + .core_reset = imx6sx_pcie_core_reset, }, [IMX6QP] = { .variant = IMX6QP, @@ -1489,6 +1495,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx_pcie_init_phy, .set_ref_clk = imx6q_pcie_set_ref_clk, + .core_reset = imx6qp_pcie_core_reset, }, [IMX7D] = { .variant = IMX7D, @@ -1502,6 +1509,7 @@ static const struct imx_pcie_drvdata drvdata[] = { .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, .init_phy = imx7d_pcie_init_phy, .set_ref_clk = imx7d_pcie_set_ref_clk, + .core_reset = imx7d_pcie_core_reset, }, [IMX8MQ] = { .variant = IMX8MQ,