From patchwork Mon Jun 17 15:07:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dragos Tatulea X-Patchwork-Id: 13700946 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2075.outbound.protection.outlook.com [40.107.101.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B45A152DF2; Mon, 17 Jun 2024 15:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.101.75 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718636970; cv=fail; b=MdThaeoXAFG5nJq1UyLZ7JmMOOD6rC8dCnl1fnofsAG7V4VzoihDK9riGtGmurtm8tzCVPSTWvzDxP84bgCvsm7dtf5x7Jnxh9tJ9540seR+pO6OjdwoIpXiEbOsZkiKrXO/DMIwC/E4/GKpgtg1R4SmyAQMHGO2deCURwEWvd0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718636970; c=relaxed/simple; bh=nTfUA3+eeP+LjaQ2b4SdWdE3/SHoPs4LUPwULAsEpKc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=hFNgCYW7p2AaEB1yM3YPu2a2GBgArYcGZg6EkG7tDn9x0ep3mebC3GUziivA1rDVI1dc9RzUqZG7sb/mtvSXMPtSsK0dI7iSmelbIklLOizG84GIRCyQJnXXK0P7XFw15chFRKZxKyKypYQtI0hKwfUCGW2ZaAmAakPqvRiY6QA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=YUJz+LgR; arc=fail smtp.client-ip=40.107.101.75 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="YUJz+LgR" ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=YUCOie/OYXHpvBOZeDLZN7CFcD8BMyAmtnoipWS3mb10msO3Y4L6+DJbjMLKLY0j0sD1x48HxNsR1Op8w6upeGTSmkmPDDQO/B2esRndZRoaTL6LrMpjmOVX6UBBQ+xoqJGAd9FL9JdWGxqv44gaR04lnunnnZL/OPSqOgkAhfI50VSOqImwyPAT6MiOWyAww6IwRDJrXuKkFp+tmBpDiDmCPpMu3QGE0y4NUdurwuhSBa6ppnEnMiJeKf5DZMoScqpuozJBaHMsQQt6Dj/3cewtVuDEa/wi7hWm9H6DoG0+pAV4VkZa15ikiw1kooH10chBLBi0ShM10XTVPAML2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=B2P/m400lrNpunlyWcf3KblMIoK4PdhXSvMi48p9v58=; b=KBHNDk+wnFgKvk9imjpBfv44+kTdWD3CoWS+zIQDPtsHg+R+StM4fAnpE28yzPPHKiiyrMBq+UoqfwF/82QHCGk7UyDW5VVNuuVGWGdA0wPRxp3t3NBRzjBrkTqQSMMwuYliYwvutqMBupUayV5VyuQG4t8WnfVAn6ZXWJQviEDL9CECw06sm1Txcd0l+2r3sRHF17+f01fFh0Bkr3bAsYIo8m/OybkQ6F3mhngFwQ8nC+7PEhbTQ4v43dNy8tk500GIitsRypZChutzSMZdqbf5RzrfV39zTWFD7RSbNjpqmzTnAhw9FyQfQuLIDTbJC5UE57BQn2Sg2T9i8Qgdpw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=redhat.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=B2P/m400lrNpunlyWcf3KblMIoK4PdhXSvMi48p9v58=; b=YUJz+LgRSGrzEQOjxMmHInObbEr9BU+zq24bbbXufdGOUIAWrycj6yQlYzba8kBAotLLZ+2aST/8oZuuAyJExISCYcvSm5BYsB+sSxls9YStzvl3ucdaG4DDmzXh/OZCNRLEUvgAF4JISRbeV8NAHV1W4vMnCwFgIAiDGA74fJYDTV80KzXuUNEpeZpVy10o4DJQgN3OE/+XsljeDfa/IG/sto3dh3K/3EMbSTCv4aW0NyATSXOY4m5xh9GzebDTFR1PnqM7497MkYyABpkvtvOGewZjI2kw5C3fGypZvM/xRyEe8lRzpT41jBwEgsf5hFsTN+ylZqS6hYie6cqMQg== Received: from SJ0PR03CA0122.namprd03.prod.outlook.com (2603:10b6:a03:33c::7) by SJ2PR12MB9239.namprd12.prod.outlook.com (2603:10b6:a03:55e::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.30; Mon, 17 Jun 2024 15:09:25 +0000 Received: from SJ1PEPF00002314.namprd03.prod.outlook.com (2603:10b6:a03:33c:cafe::41) by SJ0PR03CA0122.outlook.office365.com (2603:10b6:a03:33c::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.30 via Frontend Transport; Mon, 17 Jun 2024 15:09:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by SJ1PEPF00002314.mail.protection.outlook.com (10.167.242.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7677.15 via Frontend Transport; Mon, 17 Jun 2024 15:09:25 +0000 Received: from drhqmail201.nvidia.com (10.126.190.180) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 17 Jun 2024 08:09:06 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 17 Jun 2024 08:09:06 -0700 Received: from dev-l-177.mtl.labs.mlnx (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 17 Jun 2024 08:09:03 -0700 From: Dragos Tatulea Date: Mon, 17 Jun 2024 18:07:54 +0300 Subject: [PATCH vhost 20/23] vdpa/mlx5: Pre-create hardware VQs at vdpa .dev_add time Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20240617-stage-vdpa-vq-precreate-v1-20-8c0483f0ca2a@nvidia.com> References: <20240617-stage-vdpa-vq-precreate-v1-0-8c0483f0ca2a@nvidia.com> In-Reply-To: <20240617-stage-vdpa-vq-precreate-v1-0-8c0483f0ca2a@nvidia.com> To: "Michael S. Tsirkin" , Jason Wang , Xuan Zhuo , =?utf-8?q?Eugenio_P=C3=A9rez?= , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Si-Wei Liu CC: , , , , Dragos Tatulea , Cosmin Ratiu X-Mailer: b4 0.13.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002314:EE_|SJ2PR12MB9239:EE_ X-MS-Office365-Filtering-Correlation-Id: 0f09d0db-13e3-46d6-6d88-08dc8edf79d3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230037|376011|36860700010|82310400023|1800799021|7416011; X-Microsoft-Antispam-Message-Info: =?utf-8?q?/33UDwa/2nJQnWMfYVXBkUJRWAgQ/m6?= =?utf-8?q?zE4L+u5dzOF+w03wuGvlQyOjb7oTjYxKwYR6MZhwzYcPXcYtMvCR2NG7B9Pk3jgDC?= =?utf-8?q?l1QLUvmchMQDYcrsKwPT5WrehFwd4tyGYmvsRrNtuEXL/fo6xXVitiWOTcLauMnOf?= =?utf-8?q?LbbA1iRgvlA6kBNF0ttsmsg27IorCkiIfXU64tF+G088Mm1hajyE2wrClKvozPoJW?= =?utf-8?q?0NR27fHyfq1KLVX939TwQYeqvn2p3XkJY1IH5OGgqjRXpqmhrDll34ctFtlp+qUUV?= =?utf-8?q?u9wxPQ73Z7uLo1icaJTrrK9TSmkB034zUd42YwK5u3HSBg2quTN3GFPrLhmaT8vp5?= =?utf-8?q?yZSQJ70EfmRTPR7kcDEMgfu+u3QQKPwHFrjfNGggVdd3AYMKNK6+5fz9E/b8/JDHN?= =?utf-8?q?9n977DLwNib83/iPEUT1gfbrldgxe9d4YSO/Oam4v71zjQufthEfrMUn2O+y6TfdD?= =?utf-8?q?JnGzPVuabLttWc22K40TOPZNqjLg/NegD0RO3s8WaLR/ncFjuuuB3hjbRKxYLylJg?= =?utf-8?q?zwcQUrzuLIffNJiMEV8skf3Wr8pah9O8bh3vmwFyhza7xcuevC0g3/Qao3eFh0XjF?= =?utf-8?q?xt8BidKuA4ZHYhmnbjdnb/ox+sqC1oWFPnOxBJYsDyhreuDidRnS+7i/YYFkMw6Eg?= =?utf-8?q?aRTZjSdzbYBAw7//scM2VA+SDLF35ccQH9y7UHTunihsJ1F6qFfrObAwo7jRy1181?= =?utf-8?q?J11VQ9iIvk3jKM8O8W4ijY3QpwIb6BnFpgTKa+1ggHEku2WjBSwEclK34/nhp8rrp?= =?utf-8?q?wrJshakJhM+tGAGksSlVHdrH1P6f0ulsyHTHbqtmqKACvQEkVHiX65ouqHiX6aKPJ?= =?utf-8?q?h+bQXZ3Pnm7uvBK3MUppr0nyK5j3UGJQDdjs326HjCbo9ictApWECQ8TpYPMBXGsN?= =?utf-8?q?5ITYc00M2FWkHr5cz/lJm/HbbAjfkhsbE46wY5QCxNaUsMCuN+Kxd+qmVkTp1wVc+?= =?utf-8?q?FDvSKdajWilNy9gHhbh1Z7UtXT63+s6auJnq+s1/hcBlQ5CS5nO7HbS4E+Dze0YDz?= =?utf-8?q?mRGgn7rVpgc10qG6RTiVosW/FLaRyZpEjK8EVH4fUbaE7aShY84qHfXB76lcDZHEr?= =?utf-8?q?JYoHMmbjFKu9wgX8tKIrnAOE8SOKQoC0YISZxXg/AO6XhpWX5XXSowsgCTD9ObMiT?= =?utf-8?q?vuhNflUsywcoycwqRp9ZdNIW97VUs4Npx79NfMkLzMGGNHYDDEs6edSiJqj9PQPd7?= =?utf-8?q?l3RWRYQ2D2d6qtiEXSseyGFne0P14l+C6yYEP9gHyE7Fgmw8paeLbAlyiB+NZ4OmS?= =?utf-8?q?BnE0GXFfDUFU5gXVV1YXS7/B0tV5kYKcpE78sai1WLoPFO6E/9OafCWRNINwcpnYb?= =?utf-8?q?lNdUvaZTJDrm7HLCIsMxE+70OdCJJuvi0Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230037)(376011)(36860700010)(82310400023)(1800799021)(7416011);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jun 2024 15:09:25.2205 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0f09d0db-13e3-46d6-6d88-08dc8edf79d3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002314.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9239 Currently, hardware VQs are created right when the vdpa device gets into DRIVER_OK state. That is easier because most of the VQ state is known by then. This patch switches to creating all VQs and their associated resources at device creation time. The motivation is to reduce the vdpa device live migration downtime by moving the expensive operation of creating all the hardware VQs and their associated resources out of downtime on the destination VM. The VQs are now created in a blank state. The VQ configuration will happen later, on DRIVER_OK. Then the configuration will be applied when the VQs are moved to the Ready state. When .set_vq_ready() is called on a VQ before DRIVER_OK, special care is needed: now that the VQ is already created a resume_vq() will be triggered too early when no mr has been configured yet. Skip calling resume_vq() in this case, let it be handled during DRIVER_OK. For virtio-vdpa, the device configuration is done earlier during .vdpa_dev_add() by vdpa_register_device(). Avoid calling setup_vq_resources() a second time in that case. Signed-off-by: Dragos Tatulea Reviewed-by: Cosmin Ratiu --- drivers/vdpa/mlx5/net/mlx5_vnet.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/vdpa/mlx5/net/mlx5_vnet.c b/drivers/vdpa/mlx5/net/mlx5_vnet.c index 249b5afbe34a..b2836fd3d1dd 100644 --- a/drivers/vdpa/mlx5/net/mlx5_vnet.c +++ b/drivers/vdpa/mlx5/net/mlx5_vnet.c @@ -2444,7 +2444,7 @@ static void mlx5_vdpa_set_vq_ready(struct vdpa_device *vdev, u16 idx, bool ready mvq = &ndev->vqs[idx]; if (!ready) { suspend_vq(ndev, mvq); - } else { + } else if (mvdev->status & VIRTIO_CONFIG_S_DRIVER_OK) { if (resume_vq(ndev, mvq)) ready = false; } @@ -3078,10 +3078,18 @@ static void mlx5_vdpa_set_status(struct vdpa_device *vdev, u8 status) goto err_setup; } register_link_notifier(ndev); - err = setup_vq_resources(ndev, true); - if (err) { - mlx5_vdpa_warn(mvdev, "failed to setup driver\n"); - goto err_driver; + if (ndev->setup) { + err = resume_vqs(ndev); + if (err) { + mlx5_vdpa_warn(mvdev, "failed to resume VQs\n"); + goto err_driver; + } + } else { + err = setup_vq_resources(ndev, true); + if (err) { + mlx5_vdpa_warn(mvdev, "failed to setup driver\n"); + goto err_driver; + } } } else { mlx5_vdpa_warn(mvdev, "did not expect DRIVER_OK to be cleared\n"); @@ -3142,6 +3150,7 @@ static int mlx5_vdpa_compat_reset(struct vdpa_device *vdev, u32 flags) if (mlx5_vdpa_create_dma_mr(mvdev)) mlx5_vdpa_warn(mvdev, "create MR failed\n"); } + setup_vq_resources(ndev, false); up_write(&ndev->reslock); return 0; @@ -3836,8 +3845,21 @@ static int mlx5_vdpa_dev_add(struct vdpa_mgmt_dev *v_mdev, const char *name, goto err_reg; mgtdev->ndev = ndev; + + /* For virtio-vdpa, the device was set up during device register. */ + if (ndev->setup) + return 0; + + down_write(&ndev->reslock); + err = setup_vq_resources(ndev, false); + up_write(&ndev->reslock); + if (err) + goto err_setup_vq_res; + return 0; +err_setup_vq_res: + _vdpa_unregister_device(&mvdev->vdev); err_reg: destroy_workqueue(mvdev->wq); err_res2: @@ -3863,6 +3885,11 @@ static void mlx5_vdpa_dev_del(struct vdpa_mgmt_dev *v_mdev, struct vdpa_device * unregister_link_notifier(ndev); _vdpa_unregister_device(dev); + + down_write(&ndev->reslock); + teardown_vq_resources(ndev); + up_write(&ndev->reslock); + wq = mvdev->wq; mvdev->wq = NULL; destroy_workqueue(wq);