| Message ID | 20240627151127.284884-11-karol.kolacinski@intel.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | ice: Cleanup and refactor PTP pin handling | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Guessing tree name failed - patch did not apply |
On Thu, Jun 27, 2024 at 05:09:26PM +0200, Karol Kolacinski wrote: > Add support of PTP SDPs (Software Definable Pins) for E825C products. > > Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> ... > @@ -2623,9 +2633,13 @@ static void ice_ptp_set_funcs_e82x(struct ice_pf *pf) > pf->ptp.info.getcrosststamp = ice_ptp_getcrosststamp_e82x; > > #endif /* CONFIG_ICE_HWTS */ > - pf->ptp.info.enable = ice_ptp_gpio_enable; > - pf->ptp.info.verify = ice_verify_pin; > - pf->ptp.ice_pin_desc = ice_pin_desc_e82x; > + if (ice_is_e825c(&pf->hw)) { > + pf->ptp.ice_pin_desc = ice_pin_desc_e825c; > + pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e825c); > + } else { > + pf->ptp.ice_pin_desc = ice_pin_desc_e82x; > + pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e82x); > + } > pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e82x); Hi Karol, Maybe I'm reading it wrong, but should the line immediately above be remove to avoid overwriting the value for pf->ptp.info.n_pins set in the new if/else condition above? > ice_ptp_setup_pin_cfg(pf); > } > @@ -2673,6 +2687,8 @@ static void ice_ptp_set_caps(struct ice_pf *pf) > info->settime64 = ice_ptp_settime64; > info->n_per_out = GLTSYN_TGT_H_IDX_MAX; > info->n_ext_ts = GLTSYN_EVNT_H_IDX_MAX; > + info->enable = ice_ptp_gpio_enable; > + info->verify = ice_verify_pin; > > if (ice_is_e810(&pf->hw)) > ice_ptp_set_funcs_e810(pf, info); Moving these assignments seems unnecessary, but ok.
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 28b82c634194..e38563905ca7 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -20,6 +20,16 @@ static const struct ice_ptp_pin_desc ice_pin_desc_e82x[] = { { ONE_PPS, { 5, -1 }}, }; +static const struct ice_ptp_pin_desc ice_pin_desc_e825c[] = { + /* name, gpio */ + { SDP0, { 0, 0 }}, + { SDP1, { 1, 1 }}, + { SDP2, { 2, 2 }}, + { SDP3, { 3, 3 }}, + { TIME_SYNC, { -1, 4 }}, + { ONE_PPS, { 5, -1 }}, +}; + static const struct ice_ptp_pin_desc ice_pin_desc_e810[] = { /* name, gpio */ { SDP0, { 0, 0 }}, @@ -2623,9 +2633,13 @@ static void ice_ptp_set_funcs_e82x(struct ice_pf *pf) pf->ptp.info.getcrosststamp = ice_ptp_getcrosststamp_e82x; #endif /* CONFIG_ICE_HWTS */ - pf->ptp.info.enable = ice_ptp_gpio_enable; - pf->ptp.info.verify = ice_verify_pin; - pf->ptp.ice_pin_desc = ice_pin_desc_e82x; + if (ice_is_e825c(&pf->hw)) { + pf->ptp.ice_pin_desc = ice_pin_desc_e825c; + pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e825c); + } else { + pf->ptp.ice_pin_desc = ice_pin_desc_e82x; + pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e82x); + } pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e82x); ice_ptp_setup_pin_cfg(pf); } @@ -2673,6 +2687,8 @@ static void ice_ptp_set_caps(struct ice_pf *pf) info->settime64 = ice_ptp_settime64; info->n_per_out = GLTSYN_TGT_H_IDX_MAX; info->n_ext_ts = GLTSYN_EVNT_H_IDX_MAX; + info->enable = ice_ptp_gpio_enable; + info->verify = ice_verify_pin; if (ice_is_e810(&pf->hw)) ice_ptp_set_funcs_e810(pf, info);