From patchwork Thu Jun 27 15:09:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13714639 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C89691990AE for ; Thu, 27 Jun 2024 15:11:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719501106; cv=none; b=CLEm+dYDiG+a4lOFcDnAp15Ua2xUATvGMu0HvOQu7vR0uWLfQuRwt2DbOwdevhVdkxERcCxLYDuTK0dRZrHPF0QShKGSAwlsUzGF0Ag1u/HtIaSksWRH86XEZe8fjhLqzielXSVI9foBJE5/hfU5SJ+bBZCCYXWTN1j5GnETtC8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719501106; c=relaxed/simple; bh=u8CfDjhLIqunKUmpCLRTaaE/Tn3iMta8cQ8xuhSuzHQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UIMMAm/4rJ0DSTHmlkgyRA9b86nfmlwe2OLfgohcglwEZ1znRgBQoDFrhlXln1jSnAMScM4DA/RVhzR4Fsg6xrXrJ9uHYXL8ttLCoDQRR/AC84dvh9egJLDGzbjocW9CwBepp5JHPthFLYF1dvkJi+okyO9TFnBTBl37jg5sx6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jLapjq51; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jLapjq51" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719501104; x=1751037104; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u8CfDjhLIqunKUmpCLRTaaE/Tn3iMta8cQ8xuhSuzHQ=; b=jLapjq510Y6I9VlTJElmmjj0iyvOzWa4cut+AjO33t0XSYhRtdrRGaSM Gu9KyamcOddZOJUJbiOKQG4u48q90/27hlWYCd19f7rGLzzGZIcRFXtiX Kvt4tYurtTf+APlAYMEioa/poWADeHmS2YEB2EOUPYisiSc8o8DF7e8My hZ+W7bi56FLi2xi9r82LLjcwUw+MWr5afzko1iREJPoVHqfNsfbWG7tFS v89jXNM8RjaopLPYp1ZoxZYBa9k32OX5LAZN3yT8UDEh0JkCTUKnB/Mzn BulUbeK2YvtdpV8qgiRqWsqkGozAlFTb5TXsGZovYPnfVYHFMbMJJDfms g==; X-CSE-ConnectionGUID: 4y4fIm7iQgizFkKpRpK6pg== X-CSE-MsgGUID: ISBPC8mzTI+Oqew0xIngvg== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="27222478" X-IronPort-AV: E=Sophos;i="6.09,166,1716274800"; d="scan'208";a="27222478" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 08:11:44 -0700 X-CSE-ConnectionGUID: GBHC0kT9QtuXeDR6wLecbw== X-CSE-MsgGUID: vKrj6PiAR8Cvgo28R2HKHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,166,1716274800"; d="scan'208";a="48759685" Received: from kkolacin-desk1.igk.intel.com ([10.102.102.132]) by fmviesa003.fm.intel.com with ESMTP; 27 Jun 2024 08:11:42 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Karol Kolacinski , Arkadiusz Kubalewski Subject: [PATCH iwl-next 5/7] ice: Disable shared pin on E810 on setfunc Date: Thu, 27 Jun 2024 17:09:29 +0200 Message-ID: <20240627151127.284884-14-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240627151127.284884-9-karol.kolacinski@intel.com> References: <20240627151127.284884-9-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org When setting a new supported function for a pin on E810, disable other enabled pin that shares the same GPIO. Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Karol Kolacinski --- drivers/net/ethernet/intel/ice/ice_ptp.c | 65 ++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 82b30ea0c8bf..467675dd2693 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -1851,6 +1851,63 @@ static void ice_ptp_enable_all_perout(struct ice_pf *pf) true); } +/** + * ice_ptp_disable_shared_pin - Disable enabled pin that shares GPIO + * @pf: Board private structure + * @pin: Pin index + * @func: Assigned function + * + * Return: 0 on success, negative error code otherwise + */ +static int ice_ptp_disable_shared_pin(struct ice_pf *pf, unsigned int pin, + enum ptp_pin_function func) +{ + uint gpio_pin, i; + + switch (func) { + case PTP_PF_PEROUT: + gpio_pin = pf->ptp.ice_pin_desc[pin].gpio[1]; + break; + case PTP_PF_EXTTS: + gpio_pin = pf->ptp.ice_pin_desc[pin].gpio[0]; + break; + default: + return -EOPNOTSUPP; + } + + for (i = 0; i < pf->ptp.info.n_pins; i++) { + struct ptp_pin_desc *pin_desc = &pf->ptp.pin_desc[i]; + uint chan = pin_desc->chan; + + /* Skip pin idx from the request */ + if (i == pin) + continue; + + if (pin_desc->func == PTP_PF_PEROUT && + pf->ptp.ice_pin_desc[i].gpio[1] == gpio_pin) { + pf->ptp.perout_rqs[chan].period.sec = 0; + pf->ptp.perout_rqs[chan].period.nsec = 0; + pin_desc->func = PTP_PF_NONE; + pin_desc->chan = 0; + dev_dbg(ice_pf_to_dev(pf), "Disabling pin %u with shared output GPIO pin %u\n", + i, gpio_pin); + return ice_ptp_cfg_perout(pf, &pf->ptp.perout_rqs[chan], + false); + } else if (pf->ptp.pin_desc->func == PTP_PF_EXTTS && + pf->ptp.ice_pin_desc[i].gpio[0] == gpio_pin) { + pf->ptp.extts_rqs[chan].flags &= ~PTP_ENABLE_FEATURE; + pin_desc->func = PTP_PF_NONE; + pin_desc->chan = 0; + dev_dbg(ice_pf_to_dev(pf), "Disabling pin %u with shared input GPIO pin %u\n", + i, gpio_pin); + return ice_ptp_cfg_extts(pf, &pf->ptp.extts_rqs[chan], + false); + } + } + + return 0; +} + /** * ice_verify_pin - verify if pin supports requested pin function * @info: the driver's PTP info structure @@ -1885,6 +1942,14 @@ static int ice_verify_pin(struct ptp_clock_info *info, unsigned int pin, return -EOPNOTSUPP; } + /* On adapters with SMA_CTRL disable other pins that share same GPIO */ + if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) { + ice_ptp_disable_shared_pin(pf, pin, func); + pf->ptp.pin_desc[pin].func = func; + pf->ptp.pin_desc[pin].chan = chan; + return ice_ptp_set_sma_cfg_e810t(pf); + } + return 0; }