From patchwork Thu Jun 27 15:09:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13714641 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2D0C71991B0 for ; Thu, 27 Jun 2024 15:11:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719501109; cv=none; b=nHI2HOI3rSzEc55oqKVGYmud4edCbAOtlKOgaGQQjE//TEuNqaoLtv/hZPVnV7r3bo/krhv0ritHV/9BJLOOuSn2PmQtxDkjDQtd85nki8mr0RsJkHmjHCfyMHP2tUbODNRK1MZ4+E48htko5VGOWoRR+QhUiCLOBrkFr6m1yxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719501109; c=relaxed/simple; bh=hMdcskGxXF+YpO+jOZWzLp+sR4o8ZBFvtTssMWgqTLM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WBtrpR7KxeounK6ksuxeo1XAd8PfsxeymKvZHmGmAmu5ppiX2QkGPCfiJBjjCqg4Jom9VJ3FgJf0q0xM20qUJZB4HoKRA5HpAZyHuW1UrixJI8RSE0w02fvShSIXbkllfemqbLgX10PkpKVBLK38e1kuF7Rnjg6ArGSLaLQVdqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QL++YzgR; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QL++YzgR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1719501108; x=1751037108; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hMdcskGxXF+YpO+jOZWzLp+sR4o8ZBFvtTssMWgqTLM=; b=QL++YzgRKFyxItgMYRx/IIMpDAhE40/pmwcaBTUtejUK439tY8bxLvNX grZTQKVMqdjUsbpmZD1RJouMWToXhzEfSrIKHAnHEsEe2BvAwTAG1WE1f qj1I4brbX6zKGB/zWgDh5PkNkXe2ILQp6fyV7uVIqjBWiPoFPxPi87v/D K3O84Q+wQbN29L8kZkry7T7ynynRBAI+2XFkiv/utl1OJRXkiuAFdbhFO VN63EiDRgMMUgntdH2+7JGWGquxv1YYiVt0IDwWg5+qki+bWpIFbhgZR7 k+c5GS1Fx3pPTqFFC701E1cc+UoXDbez2OQGlG6Yi+QBRvOt+bCAu1DrC Q==; X-CSE-ConnectionGUID: zrfB6SyiRKiGYJUpIM6esw== X-CSE-MsgGUID: OpSiEAo9T2eosNPw1YR0fw== X-IronPort-AV: E=McAfee;i="6700,10204,11116"; a="27222492" X-IronPort-AV: E=Sophos;i="6.09,166,1716274800"; d="scan'208";a="27222492" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2024 08:11:48 -0700 X-CSE-ConnectionGUID: xQBLOYDtQVm9fr1BPCR4+Q== X-CSE-MsgGUID: iarNenidRxSJchasXjSezg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,166,1716274800"; d="scan'208";a="48759695" Received: from kkolacin-desk1.igk.intel.com ([10.102.102.132]) by fmviesa003.fm.intel.com with ESMTP; 27 Jun 2024 08:11:46 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Sergey Temerkhanov , Arkadiusz Kubalewski , Karol Kolacinski Subject: [PATCH iwl-next 7/7] ice: Enable 1PPS out from CGU for E825C products Date: Thu, 27 Jun 2024 17:09:31 +0200 Message-ID: <20240627151127.284884-16-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240627151127.284884-9-karol.kolacinski@intel.com> References: <20240627151127.284884-9-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org From: Sergey Temerkhanov Implement 1PPS signal enabling/disabling in CGU. The amplitude is always the maximum in this implementation Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Sergey Temerkhanov Co-developed-by: Karol Kolacinski Signed-off-by: Karol Kolacinski --- drivers/net/ethernet/intel/ice/ice_ptp.c | 10 ++++++++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 21 +++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 + 3 files changed, 32 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index d9ff94a4b293..b97ea2b61e5c 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -4,6 +4,7 @@ #include "ice.h" #include "ice_lib.h" #include "ice_trace.h" +#include "ice_cgu_regs.h" static const char ice_pin_names[][64] = { "SDP0", @@ -1708,6 +1709,15 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan, /* 0. Reset mode & out_en in AUX_OUT */ wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0); + if (ice_is_e825c(hw)) { + int err; + + /* Enable/disable CGU 1PPS output for E825C */ + err = ice_cgu_ena_pps_out(hw, !!period); + if (err) + return err; + } + /* 1. Write perout with half of required period value. * HW toggles output when source clock hits the TGT and then adds * GLTSYN_CLKO value to the target, so it ends up with 50% duty cycle. diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 07ecf2a86742..fa7cf8453b88 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -661,6 +661,27 @@ static int ice_cfg_cgu_pll_e825c(struct ice_hw *hw, return 0; } +#define ICE_ONE_PPS_OUT_AMP_MAX 3 + +/** + * ice_cgu_ena_pps_out - Enable/disable 1PPS output + * @hw: pointer to the HW struct + * @ena: Enable/disable 1PPS output + */ +int ice_cgu_ena_pps_out(struct ice_hw *hw, bool ena) +{ + union nac_cgu_dword9 dw9; + int err; + + err = ice_read_cgu_reg_e82x(hw, NAC_CGU_DWORD9, &dw9.val); + if (err) + return err; + + dw9.one_pps_out_en = ena; + dw9.one_pps_out_amp = ena * ICE_ONE_PPS_OUT_AMP_MAX; + return ice_write_cgu_reg_e82x(hw, NAC_CGU_DWORD9, dw9.val); +} + /** * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits * @hw: pointer to the HW struct diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index ff98f76969e3..382e84568256 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -331,6 +331,7 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); +int ice_cgu_ena_pps_out(struct ice_hw *hw, bool ena); bool ice_ptp_lock(struct ice_hw *hw); void ice_ptp_unlock(struct ice_hw *hw); void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd);