| Message ID | 20240701085343.3042567-3-o.rempel@pengutronix.de (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 2e3ed20c17e719cbe7b13feaa3e7c46cf6a85887 |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next,v2,1/3] net: dsa: microchip: lan9371/2: add 100BaseTX PHY support | expand |
On Mon, Jul 01, 2024 at 10:53:43AM +0200, Oleksij Rempel wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > As described by the microchip article "LAN937X - The required > configuration for the external MAC port to operate at RGMII-to-RGMII > 1Gbps link speed." [1]: > > "When VPHY is enabled, the auto-negotiation process following IEEE 802.3 > standard will be triggered and will result in RGMII-to-RGMII signal > failure on the interface because VPHY will try to poll the PHY status > that is not available in the scenario of RGMII-to-RGMII connection > (normally the link partner is usually an external processor). > > Note that when VPHY fails on accessing PHY registers, it will fall back > to 100Mbps speed, it indicates disabling VPHY is optional if you only > need the port to link at 100Mbps speed. > > Again, VPHY must and can only be disabled by writing VPHY_DISABLE bit in > the register below as there is no strapping pin for the control." > > This patch was tested on LAN9372, so far it seems to not to affect VPHY > based clock crossing optimization for the ports with integrated PHYs. > > [1]: https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> > --- > changes v2: > - reword the comment and link microchip article > --- Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
Hi Oleksij, > --- > drivers/net/dsa/microchip/lan937x_main.c | 3 +++ > drivers/net/dsa/microchip/lan937x_reg.h | 4 ++++ > 2 files changed, 7 insertions(+) > > diff --git a/drivers/net/dsa/microchip/lan937x_main.c > b/drivers/net/dsa/microchip/lan937x_main.c > index eaa862eb6b265..0606796b14856 100644 > --- a/drivers/net/dsa/microchip/lan937x_main.c > +++ b/drivers/net/dsa/microchip/lan937x_main.c > @@ -390,6 +390,9 @@ int lan937x_setup(struct dsa_switch *ds) > lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, > (SW_CLK125_ENB | SW_CLK25_ENB), true); > > + /* Disable global VPHY support. Related to CPU interface > only? */ > + ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, > SW_VPHY_DISABLE); Do we need to check the return value of ksz_rmw32? > + > return 0; > } > >
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index eaa862eb6b265..0606796b14856 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -390,6 +390,9 @@ int lan937x_setup(struct dsa_switch *ds) lan937x_cfg(dev, REG_SW_GLOBAL_OUTPUT_CTRL__1, (SW_CLK125_ENB | SW_CLK25_ENB), true); + /* Disable global VPHY support. Related to CPU interface only? */ + ksz_rmw32(dev, REG_SW_CFG_STRAP_OVR, SW_VPHY_DISABLE, SW_VPHY_DISABLE); + return 0; } diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 7ecada9240233..2f22a9d01de36 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -37,6 +37,10 @@ #define SW_CLK125_ENB BIT(1) #define SW_CLK25_ENB BIT(0) +/* 2 - PHY Control */ +#define REG_SW_CFG_STRAP_OVR 0x0214 +#define SW_VPHY_DISABLE BIT(31) + /* 3 - Operation Control */ #define REG_SW_OPERATION 0x0300