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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Tariq Toukan Subject: [PATCH net-next 05/10] net/mlx5: Add support for MTPTM and MTCTR registers Date: Fri, 5 Jul 2024 10:13:52 +0300 Message-ID: <20240705071357.1331313-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240705071357.1331313-1-tariqt@nvidia.com> References: <20240705071357.1331313-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|PH7PR12MB6977:EE_ X-MS-Office365-Filtering-Correlation-Id: 8fa2bbc3-ea97-49a6-7244-08dc9cc248fd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: 0kmwMi9nQU7zpHRIGiGrRKEaqDk5HHcLmCwHphLVQKPbOEUjdhlIN1kthH+fkVEgmkVQi46sXq4w3ERPMAXLISi6BgNyKGuWezS46PbNNQKIvDQCzKtufHVtuCb4r8jNm+vW8tHK/96+ZxJC+37Iig40pP1721r5xWamtXwEjlcz8Lkm/I1EQJ++/BkFk+3Co8GUO1hIqyfwsMTSXLu7US5ra7zBQfTvJ1dSnF9N+UCOO9/4BHunbRnix2lXR4DQYhnCDpDX9b0iymIa4Tw27HI+BuTDpaYkgMLAyFaJlhlWKbjtQUZb4RIMQ5bgENBllYLhS4d/hgUzyiPQpMeqSLyu2IjE6Q2Ng0XjJFudDuGlCB/mTe2PiCAcFdljR6A93y1twuaF19i1nf62WEkQJ9t6i6FGJR+hcJVT4FIJlxtvwavUyBDfDR5ivcMH5TbC37wUPMp+rze/3uBt3HJYF61zbGzHA7ZqRB2nT0PSRIWs978DEWwoDaNM7OHjgmJMV53mF0i8GEDK7ruy51td2SD4QLKCEnG7kBOM463KemsUCQ/L64jzdt/ssDP/8MkLFOkHiJ8IMSUSGXPGER1AQDovXBvZITlahLQYTcEbsE0Ol5iIsEXEkU/vm5iWZRizvj8RwcIn4L6FfIEaKTdP75VoGm2Pw+rGN+cA6j5hMPRthHnSFFvgfPh4EjwfkOaFYYYRV3nFGL6WpDnNHpvSobeL+V9gt/9OfXQ+mv+SfyPLXQTLfTDjtJd/dTbmCPWDg5/bGHOFmnXo2LqDYhypDQHqlrkq0o+RCoGdUn3GhRFYyL0FYM2a1ndSQBWl1x6n9b/KVRhBpucxlnO0pHV8MbhA9IQTh/Em6F8bOip9SOGwSzaSIXS7JZE5bnRl8ZseA7Bfjbpv0EJJPY1pss/gmOnDspA+VgH4tjkt5J0ivys2G0JMjAz1MUFbmUJ5J22S5/YryDSI9LvxrsAz6YsyO9bR4yOoDw+Q8tfOT9U1lfqrrZdU5T5+HaUtZQB8dNRzxLZHA6Sdl0VCViWmpdmncsApOmsRr61PSBLOqrY4gRvDYVqh648YBAjPZW9jeYtSgCUH7rF0ka8OUAhZuDHc+OwiUK7Vx8gcNe8VK7iBNj63dBd4ku5qAJp84LhJ3//gDajj9Tm2xu5ERvQmkFWe8RmCiqbwdsnUTQXQvG1Wo7qbTD42ByyArinL3qbi/Mu0KdupJgSgAIsjJ/0xaruNpkFlqj1obp34xz/+vgfTA6V5hbhYfxjfH1JjgD8ZdNLn4SfFeKsF0948FsBNsl+pvNVJP3aD2M0qbt9DPwlF9wojCsh25xEfuCMVDrlCOtraJFyGHuXxf6PPTKBrp9Azm0fihMFFzePRs0AKBVXukdJIhWfo5vtWZfAY2ovnE31qXpuNf4PZJx5CJ7YvKr09nFaSQWjzPRacugeWtQcy44F3VjediE2oEJ4/2uUFY34b X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Jul 2024 07:15:44.0519 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8fa2bbc3-ea97-49a6-7244-08dc9cc248fd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6977 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Make Management Precision Time Measurement (MTPTM) register and Management Cross Timestamp (MTCTR) register usable in mlx5 driver. Signed-off-by: Rahul Rameshbabu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/fw.c | 1 + include/linux/mlx5/device.h | 7 +++- include/linux/mlx5/driver.h | 2 + include/linux/mlx5/mlx5_ifc.h | 43 ++++++++++++++++++++ 4 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c index b61b7d966114..76ad46bf477d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c @@ -224,6 +224,7 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev) if (MLX5_CAP_GEN(dev, mcam_reg)) { mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_FIRST_128); mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9100_0x917F); + mlx5_get_mcam_access_reg_group(dev, MLX5_MCAM_REGS_0x9180_0x91FF); } if (MLX5_CAP_GEN(dev, qcam_reg)) diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index da09bfaa7b81..76ce76f13e5e 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1243,7 +1243,8 @@ enum mlx5_pcam_feature_groups { enum mlx5_mcam_reg_groups { MLX5_MCAM_REGS_FIRST_128 = 0x0, MLX5_MCAM_REGS_0x9100_0x917F = 0x2, - MLX5_MCAM_REGS_NUM = 0x3, + MLX5_MCAM_REGS_0x9180_0x91FF = 0x3, + MLX5_MCAM_REGS_NUM = 0x4, }; enum mlx5_mcam_feature_groups { @@ -1392,6 +1393,10 @@ enum mlx5_qcam_feature_groups { MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \ mng_access_reg_cap_mask.access_regs2.reg) +#define MLX5_CAP_MCAM_REG3(mdev, reg) \ + MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9180_0x91FF], \ + mng_access_reg_cap_mask.access_regs3.reg) + #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \ MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 779cfdf2e9d6..4c95bcfb76ca 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -159,6 +159,8 @@ enum { MLX5_REG_MSECQ = 0x9155, MLX5_REG_MSEES = 0x9156, MLX5_REG_MIRC = 0x9162, + MLX5_REG_MTPTM = 0x9180, + MLX5_REG_MTCTR = 0x9181, MLX5_REG_SBCAM = 0xB01F, MLX5_REG_RESOURCE_DUMP = 0xC000, MLX5_REG_DTOR = 0xC00E, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 360d42f041b0..0726022a2ecd 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -10350,6 +10350,18 @@ struct mlx5_ifc_mcam_access_reg_bits2 { u8 regs_31_to_0[0x20]; }; +struct mlx5_ifc_mcam_access_reg_bits3 { + u8 regs_127_to_96[0x20]; + + u8 regs_95_to_64[0x20]; + + u8 regs_63_to_32[0x20]; + + u8 regs_31_to_2[0x1e]; + u8 mtctr[0x1]; + u8 mtptm[0x1]; +}; + struct mlx5_ifc_mcam_reg_bits { u8 reserved_at_0[0x8]; u8 feature_group[0x8]; @@ -10362,6 +10374,7 @@ struct mlx5_ifc_mcam_reg_bits { struct mlx5_ifc_mcam_access_reg_bits access_regs; struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; + struct mlx5_ifc_mcam_access_reg_bits3 access_regs3; u8 reserved_at_0[0x80]; } mng_access_reg_cap_mask; @@ -11115,6 +11128,34 @@ struct mlx5_ifc_mtmp_reg_bits { u8 sensor_name_lo[0x20]; }; +struct mlx5_ifc_mtptm_reg_bits { + u8 reserved_at_0[0x10]; + u8 psta[0x1]; + u8 reserved_at_11[0xf]; + + u8 reserved_at_20[0x60]; +}; + +enum { + MLX5_MTCTR_REQUEST_NOP = 0x0, + MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK = 0x1, + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER = 0x2, + MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK = 0x3, +}; + +struct mlx5_ifc_mtctr_reg_bits { + u8 first_clock_timestamp_request[0x8]; + u8 second_clock_timestamp_request[0x8]; + u8 reserved_at_10[0x10]; + + u8 first_clock_valid[0x1]; + u8 second_clock_valid[0x1]; + u8 reserved_at_22[0x1e]; + + u8 first_clock_timestamp[0x40]; + u8 second_clock_timestamp[0x40]; +}; + union mlx5_ifc_ports_control_registers_document_bits { struct mlx5_ifc_bufferx_reg_bits bufferx_reg; struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; @@ -11179,6 +11220,8 @@ union mlx5_ifc_ports_control_registers_document_bits { struct mlx5_ifc_mrtc_reg_bits mrtc_reg; struct mlx5_ifc_mtcap_reg_bits mtcap_reg; struct mlx5_ifc_mtmp_reg_bits mtmp_reg; + struct mlx5_ifc_mtptm_reg_bits mtptm_reg; + struct mlx5_ifc_mtctr_reg_bits mtctr_reg; u8 reserved_at_0[0x60e0]; };