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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Rahul Rameshbabu , Carolina Jubran , Tariq Toukan Subject: [PATCH net-next V2 07/10] net/mlx5: Implement PTM cross timestamping support Date: Mon, 8 Jul 2024 11:00:22 +0300 Message-ID: <20240708080025.1593555-8-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240708080025.1593555-1-tariqt@nvidia.com> References: <20240708080025.1593555-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002320:EE_|CY5PR12MB6154:EE_ X-MS-Office365-Filtering-Correlation-Id: 702db8ae-62b7-437f-8467-08dc9f24432c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: aQRsG6KUskpanA4v+Fs0s5LjSmdBbhI4Rl4ZWyzpRsbtsUNTWERSATA0IO+pgmdaVP2KdpR115F9vYm5yeGlx3xAHA/45Wd/vWUh356HHyBq47mKOOD0cekO6sVwxjZrDm6wNZMFYWg9Euv7hzDvH8xp7h1W15omn48wHHZGq8ywKHDLJEAbaYcpaFZTeyrCVX9C4ZotidDP/NDh9KshL9ysnEsJoeGKk8l/sg4Z/Bioj9U/95TOan0OJqzmnRwtFQMjv+/gdDUYsDk0IQjhyDoXMG5orA/0gge+IHXLRB+CHKvRzZW4IOLkpGjXujDxyolBNp+ORia0KhCir+nlUhnr7KGN5b0NU/b4JhpGd+zDmeulZ46Wpkof/bSsWH/UhrlPZ7cF68JvLNFde7auAjP7j3+nOhqc7UTGbWsdDbB+eSRyIMsvZApKqiQdAORKeK4PCszMU4NRjT1c/ZPVQFRsKwiXC1aLwrHBvHf9E8NSvexXnzVDLUsL0WW7sBPEYbPYZhv0M1wnBWX/JaITr3sUAzAudqZAc0hbj4KQjkihTZWm8oC8CYaZNJ+qVoGB+bDO7c45V53+eCybD+cX9B2MmexiEWwChho7GlfFpKXXXOGqTsnU9F5lNfaORpp5z1DQpz6sDsZA3mIrX3l407HE640RAcX7CD+iRdVgVcfN363++DIJSNfc9JxN8sfCvvgvvnOLL6MNa8NtNrL0Oa5SMhApjUIeqCSJZdAtqm9DbiaULvXgGcCQMLRdP0m21UkkvZv/x1ga8ThMuD09PuBTWbMUz1D6Yuzta4Jn4yX7/0h7Gjmch+LrSQO9WHkPv6K6X6zKI3qgzRfP80ou1bJzjDCYjHRvEJHNfUb6y4WqRdjJtcvGdGENzvyBx5kIHB6V2SxQ5pHMQT0d47qS463dNl56Mv70wodmkvAuCU/UJIVyj+bQAoM3lp0SHaNkbEL1f9EsEjlGg8LlN2Ovs4kiL2B0TzvliPCulnlj/7cH+SKi2PZV1I7WqwohkHLZeuKGrDtvuuVD23/fzfBHwMyM7oEsDFjVaDFM1U3Eb3MdfSgieJde2inO1cbtWGZLGlMnQWlEND/2qvlQxAQICN8d90LlOgZNnhL9gBqLWyc92Kzr+qc9+dAZ3LBtNs927vHvS02YqisuYRqfMu/cXkYc1WU4KfH6z9AcfvM8EvvNuaYYAXRyRi6nt5nXR7zQR5GH2Ognvrz9sBwHGYe4pQzVHa/8YXQsuQ97pgz/6P+OGVsWe+enjBr2WGlSdmYSbJSsn7CVUUpBU2ZnBl7RRBfysk9pGkBY4TZ5K2T69ZyyP1jIDv+QjCcLJ977RkVVbJIk6buVeThCSKFwwmi3JgOgijx/8dSmeP8shKY/ZgMUQiMnopyVkuft/2RtPzk8iH1g0LNhuHFxOjZVYFCbXzYWoGuVUIArcFd/maJ9dfAP//49frQ6WojM9/O9BaN0 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2024 08:02:07.3929 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 702db8ae-62b7-437f-8467-08dc9f24432c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002320.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6154 X-Patchwork-Delegate: kuba@kernel.org From: Rahul Rameshbabu Expose Precision Time Measurement support through related PTP ioctl. Signed-off-by: Rahul Rameshbabu Co-developed-by: Carolina Jubran Signed-off-by: Carolina Jubran Signed-off-by: Tariq Toukan --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 88 +++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 0361741632a6..5e7bd1ce54c5 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -38,6 +38,11 @@ #include "lib/eq.h" #include "en.h" #include "clock.h" +#ifdef CONFIG_X86 +#include +#include +#include +#endif /* CONFIG_X86 */ enum { MLX5_PIN_MODE_IN = 0x0, @@ -148,6 +153,83 @@ static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) MLX5_REG_MTUTC, 0, 1); } +#ifdef CONFIG_X86 +static bool mlx5_is_ptm_source_time_available(struct mlx5_core_dev *dev) +{ + u32 out[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; + u32 in[MLX5_ST_SZ_DW(mtptm_reg)] = {0}; + int err; + + if (!MLX5_CAP_MCAM_REG3(dev, mtptm)) + return false; + + err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MTPTM, + 0, 0); + if (err) + return false; + + return !!MLX5_GET(mtptm_reg, out, psta); +} + +static int mlx5_mtctr_syncdevicetime(ktime_t *device_time, + struct system_counterval_t *sys_counterval, + void *ctx) +{ + u32 out[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; + u32 in[MLX5_ST_SZ_DW(mtctr_reg)] = {0}; + struct mlx5_core_dev *mdev = ctx; + bool real_time_mode; + u64 host, device; + int err; + + real_time_mode = mlx5_real_time_mode(mdev); + + MLX5_SET(mtctr_reg, in, first_clock_timestamp_request, + MLX5_MTCTR_REQUEST_PTM_ROOT_CLOCK); + MLX5_SET(mtctr_reg, in, second_clock_timestamp_request, + real_time_mode ? MLX5_MTCTR_REQUEST_REAL_TIME_CLOCK : + MLX5_MTCTR_REQUEST_FREE_RUNNING_COUNTER); + + err = mlx5_core_access_reg(mdev, in, sizeof(in), out, sizeof(out), MLX5_REG_MTCTR, + 0, 0); + if (err) + return err; + + if (!MLX5_GET(mtctr_reg, out, first_clock_valid) || + !MLX5_GET(mtctr_reg, out, second_clock_valid)) + return -EINVAL; + + host = MLX5_GET64(mtctr_reg, out, first_clock_timestamp); + *sys_counterval = convert_art_ns_to_tsc(host); + + device = MLX5_GET64(mtctr_reg, out, second_clock_timestamp); + if (real_time_mode) + *device_time = ns_to_ktime(REAL_TIME_TO_NS(device >> 32, device & U32_MAX)); + else + *device_time = mlx5_timecounter_cyc2time(&mdev->clock, device); + + return 0; +} + +static int mlx5_ptp_getcrosststamp(struct ptp_clock_info *ptp, + struct system_device_crosststamp *cts) +{ + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); + struct system_time_snapshot history_begin = {0}; + struct mlx5_core_dev *mdev; + + mdev = container_of(clock, struct mlx5_core_dev, clock); + + if (!mlx5_is_ptm_source_time_available(mdev)) + return -EBUSY; + + ktime_get_snapshot(&history_begin); + + return get_device_system_crosststamp(mlx5_mtctr_syncdevicetime, mdev, + &history_begin, cts); +} +#endif /* CONFIG_X86 */ + static u64 mlx5_read_time(struct mlx5_core_dev *dev, struct ptp_system_timestamp *sts, bool real_time) @@ -1034,6 +1116,12 @@ static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) if (MLX5_CAP_MCAM_REG(mdev, mtutc)) mlx5_init_timer_max_freq_adjustment(mdev); +#ifdef CONFIG_X86 + if (MLX5_CAP_MCAM_REG3(mdev, mtptm) && + MLX5_CAP_MCAM_REG3(mdev, mtctr) && boot_cpu_has(X86_FEATURE_ART)) + clock->ptp_info.getcrosststamp = mlx5_ptp_getcrosststamp; +#endif /* CONFIG_X86 */ + mlx5_timecounter_init(mdev); mlx5_init_clock_info(mdev); mlx5_init_overflow_period(clock);