From patchwork Mon Jul 15 07:11:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Justin Lai X-Patchwork-Id: 13732986 X-Patchwork-Delegate: kuba@kernel.org Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFFD82AF1E; Mon, 15 Jul 2024 07:14:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721027680; cv=none; b=Xz569W6wt5WdiFTCcuo0bWLXbHMkG5srL4jgHiiZVzBiUfyQRkAR9f5RCLkiNYYI2DCOfddEPRRXEgrlFnwsUjtvdC8d4MpDBvAsR0a2mLI5Iln0J5CZehGgbJ9D4xXabcjDV59gQJjoyxWfOtKgVfBOvVxhz16D2Mtf5EqYofc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721027680; c=relaxed/simple; bh=EnZCtQAqbQNVoUA5NSY7pkTTx1TaGjXVbrdyiKG3Pq8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=W2/r3XZ0PIoGL5yKrR83xawe/As7+JrxGDHuD2qDLluQ4JLxaypYWlKCPWO5FZFzZoIq22s2Ye/zNuE+fzorl0UFtremmMBDFs1xHKdxDo7HH7tF8gsfC8ZLCLM+mycL2M46T5Qj6k1rMOyperlBMQhGwfrQTchqfdDFyvMfj14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b=OIRqD5wF; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=realtek.com header.i=@realtek.com header.b="OIRqD5wF" X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 46F7EDtyC3485605, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=realtek.com; s=dkim; t=1721027653; bh=EnZCtQAqbQNVoUA5NSY7pkTTx1TaGjXVbrdyiKG3Pq8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=OIRqD5wFjXwe70RJR+5rG6eDNHNUQPjOS83M1zqTJUGjy7DBqoUjofo7tt+Q3FGwR i3rpMwkTb5I2oToTnssr971bywbKedPUV4m3GCS/kJabj9cfIZaQvyQV9BW+aXuiPo GVJ8480Z5OVAWSO1DTD/2HmKk5cim60oZ83WRQt8hBL5zBffznPsfvf8SiQChZJ3lf c1E3pVC2lT1AKmdMUztsQHzFaTD3WN3Dgo+NB7gGLf71kwx7zQI1fXvGQa04EaRQuB Nvt98uRnx53SgSI8327hsLw88nzVMst/KpK/FXc0TK90Ss59D+el3MxDZ+QIoZo0sA +AD8/GX8c/6AA== Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/3.02/5.92) with ESMTPS id 46F7EDtyC3485605 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 15 Jul 2024 15:14:13 +0800 Received: from RTEXMBS04.realtek.com.tw (172.21.6.97) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Mon, 15 Jul 2024 15:14:13 +0800 Received: from RTDOMAIN (172.21.210.74) by RTEXMBS04.realtek.com.tw (172.21.6.97) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.35; Mon, 15 Jul 2024 15:14:12 +0800 From: Justin Lai To: CC: , , , , , , , , , , , , "Justin Lai" Subject: [PATCH net-next v24 04/13] rtase: Implement the interrupt routine and rtase_poll Date: Mon, 15 Jul 2024 15:11:49 +0800 Message-ID: <20240715071158.110384-5-justinlai0215@realtek.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240715071158.110384-1-justinlai0215@realtek.com> References: <20240715071158.110384-1-justinlai0215@realtek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS04.realtek.com.tw (172.21.6.97) X-Patchwork-Delegate: kuba@kernel.org 1. Implement rtase_interrupt to handle txQ0/rxQ0, txQ4~txQ7 interrupts, and implement rtase_q_interrupt to handle txQ1/rxQ1, txQ2/rxQ2 and txQ3/rxQ3 interrupts. 2. Implement rtase_poll to call ring_handler to process the tx or rx packet of each ring. If the returned value is budget,it means that there is still work of a certain ring that has not yet been completed. Signed-off-by: Justin Lai --- .../net/ethernet/realtek/rtase/rtase_main.c | 69 +++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/net/ethernet/realtek/rtase/rtase_main.c b/drivers/net/ethernet/realtek/rtase/rtase_main.c index ef0b4ff5db7c..9cd45ae37590 100644 --- a/drivers/net/ethernet/realtek/rtase/rtase_main.c +++ b/drivers/net/ethernet/realtek/rtase/rtase_main.c @@ -584,6 +584,75 @@ static void rtase_hw_start(const struct net_device *dev) rtase_enable_hw_interrupt(tp); } +/* the interrupt handler does RXQ0 and TXQ0, TXQ4~7 interrutp status + */ +static irqreturn_t rtase_interrupt(int irq, void *dev_instance) +{ + const struct rtase_private *tp; + struct rtase_int_vector *ivec; + u32 status; + + ivec = dev_instance; + tp = ivec->tp; + status = rtase_r32(tp, ivec->isr_addr); + + rtase_w32(tp, ivec->imr_addr, 0x0); + rtase_w32(tp, ivec->isr_addr, status & ~RTASE_FOVW); + + if (napi_schedule_prep(&ivec->napi)) + __napi_schedule(&ivec->napi); + + return IRQ_HANDLED; +} + +/* the interrupt handler does RXQ1&TXQ1 or RXQ2&TXQ2 or RXQ3&TXQ3 interrupt + * status according to interrupt vector + */ +static irqreturn_t rtase_q_interrupt(int irq, void *dev_instance) +{ + const struct rtase_private *tp; + struct rtase_int_vector *ivec; + u16 status; + + ivec = dev_instance; + tp = ivec->tp; + status = rtase_r16(tp, ivec->isr_addr); + + rtase_w16(tp, ivec->imr_addr, 0x0); + rtase_w16(tp, ivec->isr_addr, status); + + if (napi_schedule_prep(&ivec->napi)) + __napi_schedule(&ivec->napi); + + return IRQ_HANDLED; +} + +static int rtase_poll(struct napi_struct *napi, int budget) +{ + const struct rtase_int_vector *ivec; + const struct rtase_private *tp; + struct rtase_ring *ring; + int total_workdone = 0; + + ivec = container_of(napi, struct rtase_int_vector, napi); + tp = ivec->tp; + + list_for_each_entry(ring, &ivec->ring_list, ring_entry) + total_workdone += ring->ring_handler(ring, budget); + + if (total_workdone >= budget) + return budget; + + if (napi_complete_done(napi, total_workdone)) { + if (!ivec->index) + rtase_w32(tp, ivec->imr_addr, ivec->imr); + else + rtase_w16(tp, ivec->imr_addr, ivec->imr); + } + + return total_workdone; +} + static int rtase_open(struct net_device *dev) { struct rtase_private *tp = netdev_priv(dev);