From patchwork Fri Jul 26 11:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13742675 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B982D17A932 for ; Fri, 26 Jul 2024 11:36:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721993801; cv=none; b=iq98STkdD5UytJms/T1mYZuLEIGJyI45e9Gy7jz8EX2AhCs3tlc7HAaLX5wcjbFJRhQPmBB3SNMItXntWtxczrlpSiFU/TE+Vl7Lr8PM615T6GhKcFaOgiilikJ6mtHmiNAJTrA+AQaTDle4lX/VIqyIYWd8hNwsFKcUomnZj+E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721993801; c=relaxed/simple; bh=FjMpMmIT0x18VX/rDm1YTI4HdwVyInUD/V9X5Ed6Te4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sFecZtg4VnAtNIgPRJq7Btj+5iAKMeqWVcfneUsPlC3O5MlhCN96vIjt1k5YQkIPB4iDwHwE74gVP3xdoRWq874783Gbs1toMcftanTIEvRBxnvW/SXbPnUS0A1dydva0BOqzaqV48ZpCgQjQO2YSIk/L7Vpw38PqHx1YDeMCtU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EueBcq+d; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EueBcq+d" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721993800; x=1753529800; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FjMpMmIT0x18VX/rDm1YTI4HdwVyInUD/V9X5Ed6Te4=; b=EueBcq+dU4238NASJgtDgVVdB0/i6XxE5YYpEX74XI/yATC7hRkl0jZC pT2VmIXZkH45171nub8prGUYvk//mToqc1LyKVjZ5nq805fXQvK7dzwLH uBH+94hAFq8u4uwN9ZdjtgZG+JWS+jwZjzv0hMM86Z7hG9kx9kDQKFvh/ CWojIuNiJuvLG0hPiBBfLRsc94B8AcYEhb+pg1CuL9gA9S+FHxQfjThSC xb4ZSeYbgNyhJF8drwgf69MD3UO5waJog3TFUBfHMLr3eHt1Uegeg4Gqf m9xHRZLsEEmiJn8siEkrkNXzhHYvfL79lqBCVnFl3ak/NtTelBdCeVf0k w==; X-CSE-ConnectionGUID: aIFd19vMRb2CTsYUvMGXIw== X-CSE-MsgGUID: rh9gFGRxQbqQZz+ZtQ0Q+w== X-IronPort-AV: E=McAfee;i="6700,10204,11144"; a="19743239" X-IronPort-AV: E=Sophos;i="6.09,238,1716274800"; d="scan'208";a="19743239" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Jul 2024 04:36:39 -0700 X-CSE-ConnectionGUID: VKj5vduFTTaw5IEq5B9WqA== X-CSE-MsgGUID: nfCN+aauRqqqrBqU0U+O6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,238,1716274800"; d="scan'208";a="76466889" Received: from kkolacin-desk1.igk.intel.com ([10.102.102.132]) by fmviesa002.fm.intel.com with ESMTP; 26 Jul 2024 04:36:38 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Karol Kolacinski Subject: [PATCH v4 iwl-next 2/4] ice: Process TSYN IRQ in a separate function Date: Fri, 26 Jul 2024 13:34:44 +0200 Message-ID: <20240726113631.200083-8-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240726113631.200083-6-karol.kolacinski@intel.com> References: <20240726113631.200083-6-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Simplify TSYN IRQ processing by moving it to a separate function and having appropriate behavior per PHY model, instead of multiple conditions not related to HW, but to specific timestamping modes. Reviewed-by: Przemek Kitszel Signed-off-by: Karol Kolacinski --- drivers/net/ethernet/intel/ice/ice_main.c | 18 +------ drivers/net/ethernet/intel/ice/ice_ptp.c | 60 +++++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptp.h | 6 +++ 3 files changed, 68 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c index 8ea52c4ff2b3..068b813c8586 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -3275,22 +3275,8 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data) if (oicr & PFINT_OICR_TSYN_TX_M) { ena_mask &= ~PFINT_OICR_TSYN_TX_M; - if (ice_pf_state_is_nominal(pf) && - pf->hw.dev_caps.ts_dev_info.ts_ll_int_read) { - struct ice_ptp_tx *tx = &pf->ptp.port.tx; - unsigned long flags; - u8 idx; - - spin_lock_irqsave(&tx->lock, flags); - idx = find_next_bit_wrap(tx->in_use, tx->len, - tx->last_ll_ts_idx_read + 1); - if (idx != tx->len) - ice_ptp_req_tx_single_tstamp(tx, idx); - spin_unlock_irqrestore(&tx->lock, flags); - } else if (ice_ptp_pf_handles_tx_interrupt(pf)) { - set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf->misc_thread); - ret = IRQ_WAKE_THREAD; - } + + ret = ice_ptp_ts_irq(pf); } if (oicr & PFINT_OICR_TSYN_EVNT_M) { diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 2c5397d7a686..19f6c2408ec2 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -2748,6 +2748,66 @@ enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf) } } +/** + * ice_ptp_ts_irq - Process the PTP Tx timestamps in IRQ context + * @pf: Board private structure + * + * Returns: IRQ_WAKE_THREAD if Tx timestamp read has to be handled in the bottom + * half of the interrupt and IRQ_HANDLED otherwise. + */ +irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf) +{ + struct ice_hw *hw = &pf->hw; + + switch (hw->ptp.phy_model) { + case ICE_PHY_E810: + /* E810 capable of low latency timestamping with interrupt can + * request a single timestamp in the top half and wait for + * a second LL TS interrupt from the FW when it's ready. + */ + if (hw->dev_caps.ts_dev_info.ts_ll_int_read) { + struct ice_ptp_tx *tx = &pf->ptp.port.tx; + unsigned long flags; + u8 idx; + + if (!ice_pf_state_is_nominal(pf)) + return IRQ_HANDLED; + + spin_lock_irqsave(&tx->lock, flags); + idx = find_next_bit_wrap(tx->in_use, tx->len, + tx->last_ll_ts_idx_read + 1); + if (idx != tx->len) + ice_ptp_req_tx_single_tstamp(tx, idx); + spin_unlock_irqrestore(&tx->lock, flags); + + return IRQ_HANDLED; + } + fallthrough; /* non-LL_TS E810 */ + case ICE_PHY_E82X: + case ICE_PHY_ETH56G: + /* All other devices process timestamps in the bottom half due + * to sleeping or polling. + */ + if (!ice_ptp_pf_handles_tx_interrupt(pf)) + return IRQ_HANDLED; + + set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf->misc_thread); + return IRQ_WAKE_THREAD; + case ICE_PHY_E830: + /* E830 can read timestamps in the top half using rd32() */ + if (ice_ptp_process_ts(pf) == ICE_TX_TSTAMP_WORK_PENDING) { + /* Process outstanding Tx timestamps. If there + * is more work, re-arm the interrupt to trigger again. + */ + wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M); + ice_flush(hw); + } + return IRQ_HANDLED; + default: + return IRQ_HANDLED; + } +} + /** * ice_ptp_maybe_trigger_tx_interrupt - Trigger Tx timstamp interrupt * @pf: Board private structure diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h index b8ab162a5538..5122b3a862fb 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp.h @@ -322,6 +322,7 @@ s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb); void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx); void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx); enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf); +irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf); u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc, const struct ice_pkt_ctx *pkt_ctx); @@ -360,6 +361,11 @@ static inline bool ice_ptp_process_ts(struct ice_pf *pf) return true; } +static inline irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf) +{ + return IRQ_HANDLED; +} + static inline u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc, const struct ice_pkt_ctx *pkt_ctx)