From patchwork Fri Jul 26 12:39:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Parthiban Veerasooran X-Patchwork-Id: 13742762 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE10E17CA16; Fri, 26 Jul 2024 12:39:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721997597; cv=none; b=WzGqF/EQrgIevWlfsa62HD1SXZJdvNo3B5je3a+kD5Xe1triJZ31CBRAmsPZqCjB+u5Y0dLbbUPUedOIS7Jg5tNi+bv81tpzzEWr7D1GV0K/AVdoEaBw58KJG06LH/H1r0zbTrQhR5M8MhXYxrTQG2E8XHUfn2QwNV8PosM6koE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721997597; c=relaxed/simple; bh=jvYmE+tnyPlUCgCyhjI+/EZE9ItdD0OGY+p0y6rbJhQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kVtOSoKp3LPujr1DAYf+yL6F1bLXxuR60qfciP/hbVXUaAWDEzJgLAfTYkmN7H6dJd01EGx36lttwxvTqje8cmXpjuMTkJYSu7MihySwlJzTGf+CW8xFaD/wHQm9Tmn+tHGBfhC8JcAO1OdgOUtBMtDCqeEsGHV+JV7PdiYZ0ik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=f846Wd7/; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="f846Wd7/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1721997595; x=1753533595; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jvYmE+tnyPlUCgCyhjI+/EZE9ItdD0OGY+p0y6rbJhQ=; b=f846Wd7/YUREPQl93KzuJjS3bR9NmU8iSdadnpAad2x1G9Q8K5sgZvKA nPLewSVU+BvY+XxP1GqHJi5BnfNsxSLijRggxwKh3V/wEtTQbAKKR/Nyd veQVFxtWC6eZxh2WD6LjCTJXG4xWU1Iu7VLr8MbewLkz2oBySL2yB5k9p Xu7xGyRH5hQtXlSqWxDzeb2up4ee1nfcmYw0x1y+Yd6exVaVlv6VjjrzN rW3Top0C3jXCcDv+ZjPg1BEBccnuPZAFukPQVPzlqDej5S9miqKTTuAph u6HSXZs0N3nrZw3/nI6oLbtoaEib6KpaEpQVWUHJi9pQwYBskbTziibkn A==; X-CSE-ConnectionGUID: 9QqqTNubSCyt71n4eg2Syg== X-CSE-MsgGUID: dx4gLh1TRxuekPRrHEAPrQ== X-IronPort-AV: E=Sophos;i="6.09,238,1716274800"; d="scan'208";a="32523227" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 26 Jul 2024 05:39:52 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 26 Jul 2024 05:39:42 -0700 Received: from CHE-LT-I17164LX.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Fri, 26 Jul 2024 05:39:33 -0700 From: Parthiban Veerasooran To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , , Parthiban Veerasooran Subject: [PATCH net-next v5 07/14] net: phy: microchip_t1s: add c45 direct access in LAN865x internal PHY Date: Fri, 26 Jul 2024 18:09:00 +0530 Message-ID: <20240726123907.566348-8-Parthiban.Veerasooran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240726123907.566348-1-Parthiban.Veerasooran@microchip.com> References: <20240726123907.566348-1-Parthiban.Veerasooran@microchip.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org This patch adds c45 registers direct access support in Microchip's LAN865x internal PHY. OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and C45 registers space. If the PHY is discovered via C22 bus protocol it assumes it uses C22 protocol and always uses C22 registers indirect access to access C45 registers. This is because, we don't have a clean separation between C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C45 registers direct access can't be used which can save multiple SPI bus access. To support this feature, set .read_mmd/.write_mmd in the PHY driver to call .read_c45/.write_c45 in the OPEN Alliance framework drivers/net/ethernet/oa_tc6.c Signed-off-by: Parthiban Veerasooran --- drivers/net/phy/microchip_t1s.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1s.c index 534ca7d1b061..3614839a8e51 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -268,6 +268,34 @@ static int lan86xx_read_status(struct phy_device *phydev) return 0; } +/* OPEN Alliance 10BASE-T1x compliance MAC-PHYs will have both C22 and + * C45 registers space. If the PHY is discovered via C22 bus protocol it assumes + * it uses C22 protocol and always uses C22 registers indirect access to access + * C45 registers. This is because, we don't have a clean separation between + * C22/C45 register space and C22/C45 MDIO bus protocols. Resulting, PHY C45 + * registers direct access can't be used which can save multiple SPI bus access. + * To support this feature, set .read_mmd/.write_mmd in the PHY driver to call + * .read_c45/.write_c45 in the OPEN Alliance framework + * drivers/net/ethernet/oa_tc6.c + */ +static int lan865x_phy_read_mmd(struct phy_device *phydev, int devnum, + u16 regnum) +{ + struct mii_bus *bus = phydev->mdio.bus; + int addr = phydev->mdio.addr; + + return __mdiobus_c45_read(bus, addr, devnum, regnum); +} + +static int lan865x_phy_write_mmd(struct phy_device *phydev, int devnum, + u16 regnum, u16 val) +{ + struct mii_bus *bus = phydev->mdio.bus; + int addr = phydev->mdio.addr; + + return __mdiobus_c45_write(bus, addr, devnum, regnum, val); +} + static struct phy_driver microchip_t1s_driver[] = { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1), @@ -285,6 +313,8 @@ static struct phy_driver microchip_t1s_driver[] = { .features = PHY_BASIC_T1S_P2MP_FEATURES, .config_init = lan865x_revb0_config_init, .read_status = lan86xx_read_status, + .read_mmd = lan865x_phy_read_mmd, + .write_mmd = lan865x_phy_write_mmd, .get_plca_cfg = genphy_c45_plca_get_cfg, .set_plca_cfg = genphy_c45_plca_set_cfg, .get_plca_status = genphy_c45_plca_get_status,