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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Mark Bloch , Tariq Toukan Subject: [PATCH net 4/8] net/mlx5: Lag, don't use the hardcoded value of the first port Date: Tue, 30 Jul 2024 09:16:33 +0300 Message-ID: <20240730061638.1831002-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240730061638.1831002-1-tariqt@nvidia.com> References: <20240730061638.1831002-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000013:EE_|SA3PR12MB7831:EE_ X-MS-Office365-Filtering-Correlation-Id: f961437a-082c-4fc3-adcb-08dcb05f7352 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|376014; X-Microsoft-Antispam-Message-Info: Mz2bI/ydM2j3K+xZ4eEq69iL0UuZ2bwFYM5WR29XbvadgK+PpBKixAkrMAPEN5pPZbBJzpElrjkwHczMTqeeaXzQUphoI7AH8kwmRC50UKRdn+0BiIl06+NoRP7iJTqATs+aMmsp4Yza5I7d5gpa3wpaGdFLrThbzN45lvPR/dt6fm46UQAZ/uqb2EbsTG6Or6t5bGWb0Ul/iEhpaW+OalTeSQU2+2QYdk3YysYCWCjKXGn3hfVM1CrYl9G5kEg8Tt1oJHkZqKWaXQ7dXbW6KI2Xv6qw2QYqxizazfMHJrHTJ+sZvuLwQyZF5ZgcQ7cXAxxBm6FPTeDZr8m5VctRjASbX72J20RzXuKJOXAWZe4dtjlOygxO7ZGkmHamR+7CArqM3wOKNnkYWWL58umgbLst3OxD49tWo3yacKTLyXwVil1co2K5LpfL1EfttWjLKLypjwF6lB4JkVO+JQICNjEWUfFbUBfF6cHJW7/92gfe6kTDwuISfJbgQm0YACr06bl3ebzwjMA3g99dFQFj+4xS5nXVq3wKkIMSNP+7YvhVNXwPONRnvkl+ZNnmp3XWRoD62/JN/H0MHTmvc5YNbXvzjzhZ21TlFifvMXyvCf9FF8BAzjHPmz01f9cQA9h9zYGq9CtigV4bZuI64g0Rc7aNn0ZU83Cf/8GyB8ujBMi1Gg8oGgQ9QC/FAGYQQT6+HxlnXZgiZMGgYOssplspUB7UkhVa35p/+lTSUhqZoABDw10A19kki4V+URT7d9YxGuq6XgVh9bBjurudtHLNDDsK/L+mINcFAabN6dQYHaMZ+CwIg/59mmdUPTgWZnJ6elxtB9hT0CDaAxuQ+EJSSjhjid65+WdE+q6NKLSV+JGQ+a4/CimYrYLe+KxK+lcl4jvhGmS7gSxyI1+l91u9ckQ0XDrm/3R5a1O3vxKyy/CJLvbERgq12Onw4dVITHe0xqdxTrAo3vNZZhGduhGm7Zt88uMzADWfuBFisMozhbQBZRS+mkPAQkE9GeimzkZDZYBdVPmpqdsdnOElLvro4uahc/pwYsMv/9bw3UP1c9BmmNPwgdRZe8yIQQ8jdtEooTw4c4pXFranCdvelIGmVC+I9wHrRsXd80hhHXoKxSn3iNhnPqB7eaXjUOO6S9qYQTxuBgriN+0YooBeMpyuoQhbQv/9lW/H+nlJ37ejjQoK9o4RdJoph94Xw9nH2SF2/nEcruPqvmHGq1BMwGFeJn8n6XLrnHg3belRA/8kwD2gOJrY3I/tTGcq40ZDPhDQ+8Ua5Va6JK/n21Ici5u2CoAbA7SbveTAEow2glvobJZMKkgP2S4IDXjYZVY23RI+GO0NVQXfmeFd6nh8Ep9phb13rlUamja3lQ8cNJanyhnhmCK8crcUMLuiItdYH2dVxWRO1/1W7qNfWlMh1HJlOltRfdzntJWvLrEccV1q4t/lHQVHmykGSIhFGbRoAcnG X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2024 06:18:38.1385 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f961437a-082c-4fc3-adcb-08dcb05f7352 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000013.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7831 X-Patchwork-Delegate: kuba@kernel.org From: Mark Bloch The cited commit didn't change the body of the loop as it should. It shouldn't be using MLX5_LAG_P1. Fixes: 7e978e7714d6 ("net/mlx5: Lag, use actual number of lag ports") Signed-off-by: Mark Bloch Signed-off-by: Tariq Toukan Reviewed-by: Wojciech Drewek --- drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index d0871c46b8c5..cf8045b92689 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1538,7 +1538,7 @@ u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev, goto unlock; for (i = 0; i < ldev->ports; i++) { - if (ldev->pf[MLX5_LAG_P1].netdev == slave) { + if (ldev->pf[i].netdev == slave) { port = i; break; }