From patchwork Tue Jul 30 08:24:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liju-clr Chen X-Patchwork-Id: 13746965 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCE73192B68; Tue, 30 Jul 2024 08:24:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722327896; cv=none; b=s8nci1yIyfMi+syqzxR4td0sAsY1EEwGgY/nQtwmcDDaeXgwmUashgRHBEuxQAv9+oNB0qkYkFzGIYesK4BSOQ9IFuEJ8ouG1dfMGcmxn/3AuaVTIHbPN4JxLLTUk+DUQ3a8dLysFps3sEnQBrxy7dj9ALf2CT7yIXX+UZSCbsI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722327896; c=relaxed/simple; bh=x0ltm6Hxa0Vy3+pXBDNmJpa7RUJ9bNQPo2byf7kgLPA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TNbUaOWGOwnFsJsjyjH8cGgyiCGDN+m1EukGBxTCifY2N/UxN7l0W1sJmybDiJGCBtr1JNwRFLngQoBIO+nPf+/9bOWOpAFB7uhYXs70kyrf9bvmjOCJSmPyBvw34EWArtmuMQxrLCCA9kd7cn1+hTfKkmaxAzPuk4zueECH+Pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=HvwCwp5f; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="HvwCwp5f" X-UUID: 2cbb1ddc4e4d11efb5b96b43b535fdb4-20240730 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Yu7MeJIYWqhQ2C+VVMnAZrONTm90KX0bPfn1CYipSqI=; b=HvwCwp5f+jCvMMotom8LfiBUNWv6vHuwy6Zx8vCBTbSbP08DqyeGd2n9BdMEiHIpbs8Xxi+QH82s3ytCPs/zjfK+aamV/QkeZwG4+o04Pw9s1SsTX2GIJG5NAZQIG2xkcWg9pCurdNKoArARyLJB0vJlmAqb25SER8VOKB94dJY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41,REQID:70c801b0-2ef7-4ba9-9eb3-d9b74a6ce582,IP:0,U RL:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-50 X-CID-META: VersionHash:6dc6a47,CLOUDID:8d22e245-a117-4f46-a956-71ffeac67bfa,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:1,IP:nil,UR L:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES: 1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 2cbb1ddc4e4d11efb5b96b43b535fdb4-20240730 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 2005976490; Tue, 30 Jul 2024 16:24:44 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Tue, 30 Jul 2024 01:24:38 -0700 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Tue, 30 Jul 2024 16:24:38 +0800 From: Liju-clr Chen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Corbet , Catalin Marinas , Will Deacon , Steven Rostedt , Masami Hiramatsu , Mathieu Desnoyers , Richard Cochran , Matthias Brugger , AngeloGioacchino Del Regno , Liju-clr Chen , Yingshiuan Pan , Ze-yu Wang CC: , , , , , , , Shawn Hsiao , PeiLun Suei , Chi-shen Yeh , Kevenny Hsieh Subject: [PATCH v12 12/24] virt: geniezone: Add memory region purpose for hypervisor Date: Tue, 30 Jul 2024 16:24:24 +0800 Message-ID: <20240730082436.9151-13-liju-clr.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240730082436.9151-1-liju-clr.chen@mediatek.com> References: <20240730082436.9151-1-liju-clr.chen@mediatek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N From: Jerry Wang Hypervisor might need to know the precise purpose of each memory region, so that it can provide specific memory protection. We add a new uapi to pass address and size of a memory region and its purpose. Signed-off-by: Jerry Wang Signed-off-by: Yi-De Wu Signed-off-by: Liju Chen --- arch/arm64/geniezone/gzvm_arch_common.h | 2 ++ arch/arm64/geniezone/vm.c | 10 ++++++++++ drivers/virt/geniezone/gzvm_vm.c | 7 +++++++ include/linux/soc/mediatek/gzvm_drv.h | 3 +++ 4 files changed, 22 insertions(+) diff --git a/arch/arm64/geniezone/gzvm_arch_common.h b/arch/arm64/geniezone/gzvm_arch_common.h index d4b49a4b283a..dabd11438e94 100644 --- a/arch/arm64/geniezone/gzvm_arch_common.h +++ b/arch/arm64/geniezone/gzvm_arch_common.h @@ -22,6 +22,7 @@ enum { GZVM_FUNC_PROBE = 12, GZVM_FUNC_ENABLE_CAP = 13, GZVM_FUNC_INFORM_EXIT = 14, + GZVM_FUNC_MEMREGION_PURPOSE = 15, NR_GZVM_FUNC, }; @@ -44,6 +45,7 @@ enum { #define MT_HVC_GZVM_PROBE GZVM_HCALL_ID(GZVM_FUNC_PROBE) #define MT_HVC_GZVM_ENABLE_CAP GZVM_HCALL_ID(GZVM_FUNC_ENABLE_CAP) #define MT_HVC_GZVM_INFORM_EXIT GZVM_HCALL_ID(GZVM_FUNC_INFORM_EXIT) +#define MT_HVC_GZVM_MEMREGION_PURPOSE GZVM_HCALL_ID(GZVM_FUNC_MEMREGION_PURPOSE) #define GIC_V3_NR_LRS 16 diff --git a/arch/arm64/geniezone/vm.c b/arch/arm64/geniezone/vm.c index 8690def2419f..c20a2ded2a4f 100644 --- a/arch/arm64/geniezone/vm.c +++ b/arch/arm64/geniezone/vm.c @@ -144,6 +144,16 @@ int gzvm_arch_destroy_vm(u16 vm_id) 0, 0, &res); } +int gzvm_arch_memregion_purpose(struct gzvm *gzvm, + struct gzvm_userspace_memory_region *mem) +{ + struct arm_smccc_res res; + + return gzvm_hypcall_wrapper(MT_HVC_GZVM_MEMREGION_PURPOSE, gzvm->vm_id, + mem->guest_phys_addr, mem->memory_size, + mem->flags, 0, 0, 0, &res); +} + static int gzvm_vm_arch_enable_cap(struct gzvm *gzvm, struct gzvm_enable_cap *cap, struct arm_smccc_res *res) diff --git a/drivers/virt/geniezone/gzvm_vm.c b/drivers/virt/geniezone/gzvm_vm.c index e7415d0620af..dd2de6e3bcde 100644 --- a/drivers/virt/geniezone/gzvm_vm.c +++ b/drivers/virt/geniezone/gzvm_vm.c @@ -105,6 +105,7 @@ static int gzvm_vm_ioctl_set_memory_region(struct gzvm *gzvm, struct gzvm_userspace_memory_region *mem) { + int ret; struct vm_area_struct *vma; struct gzvm_memslot *memslot; unsigned long size; @@ -128,6 +129,12 @@ gzvm_vm_ioctl_set_memory_region(struct gzvm *gzvm, memslot->vma = vma; memslot->flags = mem->flags; memslot->slot_id = mem->slot; + + ret = gzvm_arch_memregion_purpose(gzvm, mem); + if (ret) { + pr_err("Failed to config memory region for the specified purpose\n"); + return -EFAULT; + } return register_memslot_addr_range(gzvm, memslot); } diff --git a/include/linux/soc/mediatek/gzvm_drv.h b/include/linux/soc/mediatek/gzvm_drv.h index 096e72b76e5c..3c2b5d9071c6 100644 --- a/include/linux/soc/mediatek/gzvm_drv.h +++ b/include/linux/soc/mediatek/gzvm_drv.h @@ -179,6 +179,9 @@ void gzvm_drv_irqfd_exit(void); int gzvm_vm_irqfd_init(struct gzvm *gzvm); void gzvm_vm_irqfd_release(struct gzvm *gzvm); +int gzvm_arch_memregion_purpose(struct gzvm *gzvm, + struct gzvm_userspace_memory_region *mem); + int gzvm_init_ioeventfd(struct gzvm *gzvm); int gzvm_ioeventfd(struct gzvm *gzvm, struct gzvm_ioeventfd *args); bool gzvm_ioevent_write(struct gzvm_vcpu *vcpu, __u64 addr, int len,