From patchwork Wed Aug 14 13:05:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13763479 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9A311B14FB for ; Wed, 14 Aug 2024 13:09:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723640969; cv=none; b=I4zA5TMnIgVDdNop/HkH9dJJsRHMomGUOr+Uxs/1+LLfrkS7aLi+0j7ry3liyin8sQCaV9abeLfr8+HtSPG5zdulKyPcnhd+AD2p6q0LnunK1HYm6FF5Jh83dJb94E23JkfOxcDszOxx9p3Z/nyTKwHbvsWXllX6G7iMX9VkecE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723640969; c=relaxed/simple; bh=ccUycTBkR5zXHgkraI6V9rtWVprTFQUObzP/IBNQB74=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M2hGOfWyOHDYHcr8Xq4rLgG3bdjO68TebBrNPUy4Qpi0SbYnzIIDQVQDGZF/xRUL+ezOw/S1OxiSILJSk2qGFm0RdJIq3eWPX3UIgydhf5jCtz+OF0/ADFAHbisjCv4KThAiFlJV6HcCJc2f1DuuttUEuyPZ74pZSFcSYIhXx7o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aSgNElDt; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aSgNElDt" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723640967; x=1755176967; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ccUycTBkR5zXHgkraI6V9rtWVprTFQUObzP/IBNQB74=; b=aSgNElDtOSD/9Wj32mIp4pqNYpMpZZ8GrsfpyGVEMYITmaabixOUlYsS Q9v92FcdwBVQu2kMZ3wqZ3czly5dnG9oBE5o289zpvDXqP82zhXJJCahZ /ITXJYQO6aell3jA0W9WglH+61opowQhM/gPNSsGh06Uh+/RuvisHeUvQ LjcPo0yw63ibDjNjw3Ey+3z+UwAaGo/Q832EHsADBWV8h/+L9kUZoHZOT +yolCHnr3o9rniA7WPKjLsTseqbqYI9pbnmJtfFMqja6NVbEpymlt0vN0 Tl3WdQPHzf9CHJlhkE63TnFFWUZuFWrovtxGgb2JmHUXmzVPnnM6tZ53y Q==; X-CSE-ConnectionGUID: hZBpkkJ9RZuyppfLvfaTDA== X-CSE-MsgGUID: ccKbx1gaRKmWLofGl1FU1w== X-IronPort-AV: E=McAfee;i="6700,10204,11164"; a="25658766" X-IronPort-AV: E=Sophos;i="6.10,145,1719903600"; d="scan'208";a="25658766" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Aug 2024 06:09:27 -0700 X-CSE-ConnectionGUID: lYvpzWaxQ9m4HtVtDD169g== X-CSE-MsgGUID: TVmZGnaGThWi6v5oLWJl0g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,145,1719903600"; d="scan'208";a="59009643" Received: from unknown (HELO kkolacin-desk1.igk.intel.com) ([10.217.160.108]) by fmviesa009.fm.intel.com with ESMTP; 14 Aug 2024 06:09:25 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Karol Kolacinski Subject: [PATCH v6 iwl-next 2/6] ice: Use FIELD_PREP for timestamp values Date: Wed, 14 Aug 2024 15:05:40 +0200 Message-ID: <20240814130918.58444-10-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240814130918.58444-8-karol.kolacinski@intel.com> References: <20240814130918.58444-8-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Instead of using shifts and casts, use FIELD_PREP after reading 40b timestamp values. Signed-off-by: Karol Kolacinski --- V5 -> V6: Replaced removed macros with the new ones drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 ++++++--- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 13 +++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 00c6483dbffc..25d4399a7966 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1520,7 +1520,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -3199,7 +3200,8 @@ ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -4952,7 +4954,8 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) /* For E810 devices, the timestamp is reported with the lower 32 bits * in the low register, and the upper 8 bits in the high register. */ - *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); return 0; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 8a28155b206f..df94230d820f 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -673,15 +673,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw) /* Source timer incval macros */ #define INCVAL_HIGH_M 0xFF -/* Timestamp block macros */ +/* PHY 40b registers macros */ +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) +#define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32) +#define PHY_40B_LOW_M GENMASK(7, 0) +#define PHY_40B_HIGH_M GENMASK_ULL(39, 8) #define TS_VALID BIT(0) -#define TS_LOW_M 0xFFFFFFFF -#define TS_HIGH_M 0xFF -#define TS_HIGH_S 32 - -#define TS_PHY_LOW_M 0xFF -#define TS_PHY_HIGH_M 0xFFFFFFFF -#define TS_PHY_HIGH_S 8 #define BYTES_PER_IDX_ADDR_L_U 8 #define BYTES_PER_IDX_ADDR_L 4