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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 04/10] net/mlx5: hw counters: Drop unneeded cacheline alignment Date: Thu, 15 Aug 2024 08:46:50 +0300 Message-ID: <20240815054656.2210494-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240815054656.2210494-1-tariqt@nvidia.com> References: <20240815054656.2210494-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000055DE:EE_|DM6PR12MB4123:EE_ X-MS-Office365-Filtering-Correlation-Id: 77fec92e-6081-4a2b-cfbc-08dcbcf2f257 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: 0KdI5VVMT24f/Bls83pTkVJGOK82Ysyf7OAOrnBrT9BMFyJrkGMEt76P+nejLFw4x3CpJ4xL5kezvNukQvIG3uUbSA3L4MaTPsF4gmdOOs3PpZvkVKMl2IL2GqNQX8uvzmWvXv2Uxeyief+d9t5FaoM7z1hqM4V8KWDjIRloy/1EQEYAG45aAxjLUvhjdV5z9LYRzOFort6CJkZM2TaiW5JB5jTWwJEoKXZlaB0S7fCcoTWh4ab69kGOYtpBMSOixGKDnkbSLjo0lcGlJTtecJbNnqrdulHtfCkfvEqrO8xL4e0EBodgc15epKIrEp+8cfmdTP5+UbXp2kOz2UEowF3E6U72oBnU1dJVQi5TJPxU7iKtf6ZdSjjIDyr2C5l0OUZPZGHwnGEEOlUY3seM9BD5vHDMuaTnVL3eNwSOZ5Y++UrdCRH0l3U5WxC/rA6Sw64g4CIpguUptYq5yBK1JzHS548uVi0Ssx/Cqm8apSmaSvMk6bNAqcaSblB0InxSBxgjyhtr7bD3Re7JhR5csiyJSygIl4YskP55hVs/oHoXVxOfwQjiVaH5JYtzJcsSSUGKdFbib6yVCzJjy8Y2GeT38hZ3afKPiBkzRXSaK8Tw98oT1Lp+hB6K5mpWA6nGKfoHve+9+8uyJe8OlVVCoWzHwK7eVDwks0b8QxJo0lx6RYfBzJQENsGN3gD+b/dOlvikXm3cqUUNqNHcMcnErkFcok5jW2AqW2QKRLbRMAIt2uexfPCdQLE2zAOsO7Nyv+vU4rO3VqK+wTqiTIpa5GNgDWemq5b7imHcNiIJjPchYWyc6g6H4iUTRnyojR//T1e/ENs2bxdN8pHd7G2K27/GILPPwCk3F47DvqUzF7VXGETczZw6Hb+zMd/XJYaUqmlVVBvmtJL0vEBd+YkGgA9/1xciEVYBtOVqyLaIQyci8o2asU2hucz8V5ZLUY/nzPAjK/b07MWu7sL2/TUK+BxqfA7FvuYLjKBbKZC6gSCasQSWKL1SYFprC7miVcBTKVLg33nyhEWjk2pEpdxYr3pAGwzMPPyVl+Ly+k7dkPPUGApkTA6Lb2mFy18TUPXB4zsZvyvdDYV802tI/Oh66CEJJfwf5c6i81eHqMc09k43J3gAIyC02feBZjIEjqL4/O2wlNTGslUqJLY0Zn/w1a3c8yUQE4oG1PB0l+md6+vUBzu+gF7k0hYkI294rDyvuyvLA55cBvgmr0MBb04c/y71jS4NmQK4b5zEFd3CWVtdnCPU/d6bHYszIZWxDvVdpqOteKpEigF8anAr9d4DhKb9QqKuYNXeWv+y8TcMGvg1qoMp7pdR5qHvN7x+VM92iLhQMiq0wT/eEnrmKL2XG8etBGP1UfRfw/p7KVGk8NmbjRIybkIMM6h+U0VaA/m7yisTPYjt8xJQuEv2bG2YlyQWQIBXDtcSGBcheMgopiR68xWk7cLyLs045ztuZSdM X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Aug 2024 06:24:41.1372 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77fec92e-6081-4a2b-cfbc-08dcbcf2f257 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000055DE.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4123 X-Patchwork-Delegate: kuba@kernel.org From: Cosmin Ratiu The mlx5_fc struct has a cache for values queried from hw, which is cacheline aligned. On x86_64, this results in: struct mlx5_fc { u32 id; /* 0 4 */ bool aging; /* 4 1 */ /* XXX 3 bytes hole, try to pack */ struct mlx5_fc_bulk * bulk; /* 8 8 */ /* XXX 48 bytes hole, try to pack */ /* --- cacheline 1 boundary (64 bytes) --- */ struct mlx5_fc_cache cache __attribute__((__aligned__(64))); /* 64 24 */ u64 lastpackets; /* 88 8 */ u64 lastbytes; /* 96 8 */ /* size: 128, cachelines: 2, members: 6 */ /* sum members: 53, holes: 2, sum holes: 51 */ /* padding: 24 */ /* forced aligns: 1, forced holes: 1, sum forced holes: 48 */ } __attribute__((__aligned__(64))); (output from pahole). ...So a 48+24=72 byte waste. As far as I can determine, this serves no purpose other than maybe making sure that the values in the cache do not span two cachelines in the worst case scenario, but that's not a valid enough reason to waste 72 bytes per counter, especially since this code is not performance-critical. There could potentially be hundreds of thousands of counters (e.g. for connection-tracking), so this quickly adds up to multiple MB wasted. This commit removes the alignment, resulting in: struct mlx5_fc { [...] /* size: 56, cachelines: 1, members: 6 */ /* sum members: 53, holes: 1, sum holes: 3 */ /* last cacheline: 56 bytes */ }; Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c b/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c index 05d9351ff577..ef13941e55c2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_counters.c @@ -53,7 +53,7 @@ struct mlx5_fc { u32 id; bool aging; struct mlx5_fc_bulk *bulk; - struct mlx5_fc_cache cache ____cacheline_aligned_in_smp; + struct mlx5_fc_cache cache; /* last{packets,bytes} are used for calculating deltas since last reading. */ u64 lastpackets; u64 lastbytes;