From patchwork Tue Aug 20 10:21:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13769869 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BB7618EFF9 for ; Tue, 20 Aug 2024 10:24:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149478; cv=none; b=INscFATqbyBfH3y0nJMRraiVsbHQbjlT9wREMjVhXKY4oXnWYQHaAoXCrF8VoiyjsLGXmYhhtnBNKCQTLgOrHXYG7zEsY9x3NnHPC7NwotaMu4Ho4RR/Ww35xTJbgjZn13XC+sLbxWC8pTi+0683OkSa6qejG2uW8AXHjeJilFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724149478; c=relaxed/simple; bh=l5gzxvAHkcsYTsb/SkIt4xOj3KHwHOIMG4oNarMbwhk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TwKP6kJlO0AskIP4xotZdZ//tiHTy7TL8TGRKXALH+qNsTrl4CsOKSmnL9MMPzfpyorzkCpHkLyXxAl3p0icSDGzgY+1hpq+W/TAoSEUG9iHHrzANsIfm8UpuUWO5Rpp5IdRGl3FBO2Si5FCjemmzGCClXZHISnS/Jg7Y4U2M20= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CebCFhre; arc=none smtp.client-ip=198.175.65.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CebCFhre" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724149477; x=1755685477; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l5gzxvAHkcsYTsb/SkIt4xOj3KHwHOIMG4oNarMbwhk=; b=CebCFhreDE3a37tFYJZUoFwCDfIvuwyabZQp+fs8hamtPQ0xUxgE0OOo bPk6tF1jitkdi1fr3EEh70Nx5yjp0Ng6EBLzOYs+Ysfp0ZMF1/6FFvSa1 9kIcRpGZSL1+7qTjbgzXwoAuM3jVLWeI8mzZeZvyT44MtCmMFFGGXtJ+K TgUQ1LkMmmUngII3J2eOPvgJ9HB1zxkKUw+/swjP15l6oHnXKX/kmwi7m NIBn6NDKjgIc7DW6PEI5ZhnE5doEoXzy4Cam0uaZdPudtSqM1KvkwViyq R8LDVp5aoRlHWGB/mHrXKCbX4AubcsAKXvetm1UD4y6OqmgCaWrWAH6Tw g==; X-CSE-ConnectionGUID: Nd6o76m7RLuQ+f4IkGG1VQ== X-CSE-MsgGUID: dz7etoVHSdWZ3/H8c6UPFw== X-IronPort-AV: E=McAfee;i="6700,10204,11169"; a="44962825" X-IronPort-AV: E=Sophos;i="6.10,161,1719903600"; d="scan'208";a="44962825" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2024 03:24:36 -0700 X-CSE-ConnectionGUID: Th9+8xN2S8aHxWBu9sOxQg== X-CSE-MsgGUID: twTN+My5RnGssFTK7JeP+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,161,1719903600"; d="scan'208";a="98152831" Received: from unknown (HELO kkolacin-desk1.igk.intel.com) ([10.217.160.108]) by orviesa001.jf.intel.com with ESMTP; 20 Aug 2024 03:24:34 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Karol Kolacinski Subject: [PATCH v7 iwl-next 4/6] ice: Process TSYN IRQ in a separate function Date: Tue, 20 Aug 2024 12:21:51 +0200 Message-ID: <20240820102402.576985-12-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240820102402.576985-8-karol.kolacinski@intel.com> References: <20240820102402.576985-8-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Simplify TSYN IRQ processing by moving it to a separate function and having appropriate behavior per PHY model, instead of multiple conditions not related to HW, but to specific timestamping modes. Reviewed-by: Przemek Kitszel Signed-off-by: Karol Kolacinski --- drivers/net/ethernet/intel/ice/ice_main.c | 18 +------ drivers/net/ethernet/intel/ice/ice_ptp.c | 59 +++++++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_ptp.h | 6 +++ 3 files changed, 67 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c index 6f3ce0893cd9..9108613dcac3 100644 --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c @@ -3257,22 +3257,8 @@ static irqreturn_t ice_misc_intr(int __always_unused irq, void *data) if (oicr & PFINT_OICR_TSYN_TX_M) { ena_mask &= ~PFINT_OICR_TSYN_TX_M; - if (ice_pf_state_is_nominal(pf) && - pf->hw.dev_caps.ts_dev_info.ts_ll_int_read) { - struct ice_ptp_tx *tx = &pf->ptp.port.tx; - unsigned long flags; - u8 idx; - - spin_lock_irqsave(&tx->lock, flags); - idx = find_next_bit_wrap(tx->in_use, tx->len, - tx->last_ll_ts_idx_read + 1); - if (idx != tx->len) - ice_ptp_req_tx_single_tstamp(tx, idx); - spin_unlock_irqrestore(&tx->lock, flags); - } else if (ice_ptp_pf_handles_tx_interrupt(pf)) { - set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf->misc_thread); - ret = IRQ_WAKE_THREAD; - } + + ret = ice_ptp_ts_irq(pf); } if (oicr & PFINT_OICR_TSYN_EVNT_M) { diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index cf3b02d14b19..861f6224540a 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -2760,6 +2760,65 @@ enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf) } } +/** + * ice_ptp_ts_irq - Process the PTP Tx timestamps in IRQ context + * @pf: Board private structure + * + * Return: IRQ_WAKE_THREAD if Tx timestamp read has to be handled in the bottom + * half of the interrupt and IRQ_HANDLED otherwise. + */ +irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf) +{ + struct ice_hw *hw = &pf->hw; + + switch (hw->mac_type) { + case ICE_MAC_E810: + /* E810 capable of low latency timestamping with interrupt can + * request a single timestamp in the top half and wait for + * a second LL TS interrupt from the FW when it's ready. + */ + if (hw->dev_caps.ts_dev_info.ts_ll_int_read) { + struct ice_ptp_tx *tx = &pf->ptp.port.tx; + u8 idx; + + if (!ice_pf_state_is_nominal(pf)) + return IRQ_HANDLED; + + spin_lock(&tx->lock); + idx = find_next_bit_wrap(tx->in_use, tx->len, + tx->last_ll_ts_idx_read + 1); + if (idx != tx->len) + ice_ptp_req_tx_single_tstamp(tx, idx); + spin_unlock(&tx->lock); + + return IRQ_HANDLED; + } + fallthrough; /* non-LL_TS E810 */ + case ICE_MAC_GENERIC: + case ICE_MAC_GENERIC_3K_E825: + /* All other devices process timestamps in the bottom half due + * to sleeping or polling. + */ + if (!ice_ptp_pf_handles_tx_interrupt(pf)) + return IRQ_HANDLED; + + set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf->misc_thread); + return IRQ_WAKE_THREAD; + case ICE_MAC_E830: + /* E830 can read timestamps in the top half using rd32() */ + if (ice_ptp_process_ts(pf) == ICE_TX_TSTAMP_WORK_PENDING) { + /* Process outstanding Tx timestamps. If there + * is more work, re-arm the interrupt to trigger again. + */ + wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M); + ice_flush(hw); + } + return IRQ_HANDLED; + default: + return IRQ_HANDLED; + } +} + /** * ice_ptp_maybe_trigger_tx_interrupt - Trigger Tx timstamp interrupt * @pf: Board private structure diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h index b8ab162a5538..5122b3a862fb 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp.h @@ -322,6 +322,7 @@ s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb); void ice_ptp_req_tx_single_tstamp(struct ice_ptp_tx *tx, u8 idx); void ice_ptp_complete_tx_single_tstamp(struct ice_ptp_tx *tx); enum ice_tx_tstamp_work ice_ptp_process_ts(struct ice_pf *pf); +irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf); u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc, const struct ice_pkt_ctx *pkt_ctx); @@ -360,6 +361,11 @@ static inline bool ice_ptp_process_ts(struct ice_pf *pf) return true; } +static inline irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf) +{ + return IRQ_HANDLED; +} + static inline u64 ice_ptp_get_rx_hwts(const union ice_32b_rx_flex_desc *rx_desc, const struct ice_pkt_ctx *pkt_ctx)