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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000075F0.mail.protection.outlook.com (10.167.249.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7897.11 via Frontend Transport; Thu, 22 Aug 2024 20:43:23 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 22 Aug 2024 15:43:21 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V4 10/12] PCI/TPH: Add pci=nostmode to force TPH No ST Mode Date: Thu, 22 Aug 2024 15:41:18 -0500 Message-ID: <20240822204120.3634-11-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240822204120.3634-1-wei.huang2@amd.com> References: <20240822204120.3634-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F0:EE_|SA0PR12MB7089:EE_ X-MS-Office365-Filtering-Correlation-Id: 600e753c-2e11-4817-d178-08dcc2eb1118 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2024 20:43:23.8147 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 600e753c-2e11-4817-d178-08dcc2eb1118 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7089 When "No ST mode" is enabled, endpoint devices can generate TPH headers but with all steering tags treated as zero. A steering tag of zero is interpreted as "using the default policy" by the root complex. This is essential to quantify the benefit of Steering Tags for some given workloads. Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- Documentation/admin-guide/kernel-parameters.txt | 3 +++ drivers/pci/pci.c | 2 ++ drivers/pci/pci.h | 2 ++ drivers/pci/pcie/tph.c | 12 ++++++++++++ 4 files changed, 19 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index f1384c7b59c9..ed2ee97cf7fb 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4617,6 +4617,9 @@ nomio [S390] Do not use MIO instructions. norid [S390] ignore the RID field and force use of one PCI domain per PCI function + nostmode [PCIE] If PCIe TPH Processing Hints (TPH) is + enabled, this kernel option forces all Steering + Tags to be treated as zero (aka "No ST Mode"). pcie_aspm= [PCIE] Forcibly enable or ignore PCIe Active State Power Management. diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 1e4960994b1a..88aabac354c0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -6870,6 +6870,8 @@ static int __init pci_setup(char *str) pci_no_domains(); } else if (!strncmp(str, "noari", 5)) { pcie_ari_disabled = true; + } else if (!strncmp(str, "nostmode", 8)) { + pci_tph_set_nostmode(); } else if (!strncmp(str, "cbiosize=", 9)) { pci_cardbus_io_size = memparse(str + 9, &str); } else if (!strncmp(str, "cbmemsize=", 10)) { diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index d7c7f86e8705..54d74f5ff861 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -574,10 +574,12 @@ static inline int pci_iov_bus_range(struct pci_bus *bus) #ifdef CONFIG_PCIE_TPH void pci_restore_tph_state(struct pci_dev *dev); void pci_save_tph_state(struct pci_dev *dev); +void pci_tph_set_nostmode(void); void pci_tph_init(struct pci_dev *dev); #else static inline void pci_restore_tph_state(struct pci_dev *dev) { } static inline void pci_save_tph_state(struct pci_dev *dev) { } +static inline void pci_tph_set_nostmode(void) { } static inline void pci_tph_init(struct pci_dev *dev) { } #endif diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index b228ef5b7948..f723352adcf5 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -48,6 +48,8 @@ union st_info { u64 value; }; +static bool pci_tph_nostmode; + static u16 tph_extract_tag(enum tph_mem_type mem_type, u8 req_type, union st_info *info) { @@ -433,6 +435,10 @@ int pcie_enable_tph(struct pci_dev *pdev, int mode) return -EINVAL; } + /* Honor "nostmode" kernel parameter */ + if (pci_tph_nostmode) + pdev->tph_mode = PCI_TPH_NO_ST_MODE; + /* Get req_type supported by device and its Root Port */ reg = pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®); if (FIELD_GET(PCI_TPH_CAP_EXT_TPH, reg)) @@ -545,6 +551,12 @@ void pci_save_tph_state(struct pci_dev *pdev) } } +void pci_tph_set_nostmode(void) +{ + pci_tph_nostmode = true; + pr_info("PCIe TPH No ST Mode is enabled\n"); +} + void pci_tph_init(struct pci_dev *pdev) { pdev->tph_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_TPH);