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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000075F0.mail.protection.outlook.com (10.167.249.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7897.11 via Frontend Transport; Thu, 22 Aug 2024 20:42:02 +0000 Received: from weiserver.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 22 Aug 2024 15:42:00 -0500 From: Wei Huang To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH V4 03/12] PCI/TPH: Add pcie_tph_modes() to query TPH modes Date: Thu, 22 Aug 2024 15:41:11 -0500 Message-ID: <20240822204120.3634-4-wei.huang2@amd.com> X-Mailer: git-send-email 2.45.1 In-Reply-To: <20240822204120.3634-1-wei.huang2@amd.com> References: <20240822204120.3634-1-wei.huang2@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F0:EE_|SJ0PR12MB7476:EE_ X-MS-Office365-Filtering-Correlation-Id: b8b90676-c708-45a8-1499-08dcc2eae09a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2024 20:42:02.4379 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8b90676-c708-45a8-1499-08dcc2eae09a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7476 Add pcie_tph_modes() to allow drivers to query the TPH modes supported by an endpoint device, as reported in the TPH Requester Capability register. The modes are reported as a bitmask and current supported modes include: - PCI_TPH_CAP_NO_ST: NO ST Mode Supported - PCI_TPH_CAP_INT_VEC: Interrupt Vector Mode Supported - PCI_TPH_CAP_DEV_SPEC: Device Specific Mode Supported Co-developed-by: Eric Van Tassell Signed-off-by: Eric Van Tassell Signed-off-by: Wei Huang Reviewed-by: Ajit Khaparde Reviewed-by: Somnath Kotur Reviewed-by: Andy Gospodarek --- drivers/pci/pcie/tph.c | 33 +++++++++++++++++++++++++++++++++ include/linux/pci-tph.h | 18 ++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 include/linux/pci-tph.h diff --git a/drivers/pci/pcie/tph.c b/drivers/pci/pcie/tph.c index a547858c3f68..a28dced3097d 100644 --- a/drivers/pci/pcie/tph.c +++ b/drivers/pci/pcie/tph.c @@ -6,9 +6,42 @@ * Eric Van Tassell * Wei Huang */ +#include +#include #include "../pci.h" +static u8 get_st_modes(struct pci_dev *pdev) +{ + u32 reg; + + pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CAP, ®); + reg &= PCI_TPH_CAP_NO_ST | PCI_TPH_CAP_INT_VEC | PCI_TPH_CAP_DEV_SPEC; + + return reg; +} + +/** + * pcie_tph_modes - Get the ST modes supported by device + * @pdev: PCI device + * + * Returns a bitmask with all TPH modes supported by a device as shown in the + * TPH capability register. Current supported modes include: + * PCI_TPH_CAP_NO_ST - NO ST Mode Supported + * PCI_TPH_CAP_INT_VEC - Interrupt Vector Mode Supported + * PCI_TPH_CAP_DEV_SPEC - Device Specific Mode Supported + * + * Return: 0 when TPH is not supported, otherwise bitmask of supported modes + */ +int pcie_tph_modes(struct pci_dev *pdev) +{ + if (!pdev->tph_cap) + return 0; + + return get_st_modes(pdev); +} +EXPORT_SYMBOL(pcie_tph_modes); + void pci_tph_init(struct pci_dev *pdev) { pdev->tph_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_TPH); diff --git a/include/linux/pci-tph.h b/include/linux/pci-tph.h new file mode 100644 index 000000000000..fa378afe9c7e --- /dev/null +++ b/include/linux/pci-tph.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * TPH (TLP Processing Hints) + * + * Copyright (C) 2024 Advanced Micro Devices, Inc. + * Eric Van Tassell + * Wei Huang + */ +#ifndef LINUX_PCI_TPH_H +#define LINUX_PCI_TPH_H + +#ifdef CONFIG_PCIE_TPH +int pcie_tph_modes(struct pci_dev *pdev); +#else +static inline int pcie_tph_modes(struct pci_dev *pdev) { return 0; } +#endif + +#endif /* LINUX_PCI_TPH_H */