From patchwork Tue Aug 27 12:50:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13779534 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A3161C689B for ; Tue, 27 Aug 2024 13:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724764122; cv=none; b=Io/8xibHCHg9hJjxIiZZmEhtDt6BgRnpdYoka7YuVquX7cNX5nZAAS/9Lr2PtjWGFCH9jXe4yZpR0ONX24i8rongj/8i6peApmW4ballwBRKjRLHO5BXjckb640QPighIyOG42YLYSWe1kVT73AiDHeDvA7klLyLvrlFqwkVl/I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1724764122; c=relaxed/simple; bh=2mQSaneFaAvse1S7g/x7TBTbL628yvuAB8xbMvb2QkY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WvtuJ+5enBtBBr4Fk7nfm4VQ+Q80MwCFLZ44IakKoyrxoOE/uX+Yd6AhFS74PTiExS4h/apVJ66nBbxXzQHgZTFkrugiXTFjleK9qmqi2lR+qT4bYI88XOEIIsMbVLi9w9IRtSBuE0hpc9Q4+QdX1t3vYnzaMSvco0TRpwwFmqg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B/DQIkD1; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B/DQIkD1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724764120; x=1756300120; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2mQSaneFaAvse1S7g/x7TBTbL628yvuAB8xbMvb2QkY=; b=B/DQIkD1J7eOdumVT0BPmE/tQ8HxWmPUrwp9yLXWKjKeW9E7IT4yeLkv WLElNsyKCjOtUi0mpwoKl1dag0Ghn2LYF5ChCqUsyRRdHHsRku9MTYra1 ez7rvcl8upDL//7cXvLB7QU9WeR6/OVkkdVyzORYDT+2guAQv6gV0UtTt UM4ZjRRShPfQtco7aQAaIFeQMkb6JyQse5Xk/isI1ON7XUSs7BKtUC174 DNgitiUqdaeYclHsb9XfR7wakkCV6S7qPMQ8dblSi1DmJjveTUXTbaBZp ++mkpaLWYItZ7bXj95340DGl2pzSxFG5AVymy2vyemX8saikiqQ+J4BYH A==; X-CSE-ConnectionGUID: dm1Tgm0GTOmV+/DEk4/+uQ== X-CSE-MsgGUID: UI0bFnZkSLWLHfTws39inQ== X-IronPort-AV: E=McAfee;i="6700,10204,11176"; a="40710296" X-IronPort-AV: E=Sophos;i="6.10,180,1719903600"; d="scan'208";a="40710296" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2024 06:08:40 -0700 X-CSE-ConnectionGUID: JuIon/ozThWoFiQaYizpyg== X-CSE-MsgGUID: 2RKmWybiTDC7cDyANBXZ3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,180,1719903600"; d="scan'208";a="93650100" Received: from kkolacin-desk1.ger.corp.intel.com (HELO kkolacin-desk1.igk.intel.com) ([10.217.160.108]) by fmviesa001.fm.intel.com with ESMTP; 27 Aug 2024 06:08:37 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Karol Kolacinski , Simon Horman Subject: [PATCH v8 iwl-next 3/7] ice: Use FIELD_PREP for timestamp values Date: Tue, 27 Aug 2024 14:50:45 +0200 Message-ID: <20240827130814.732181-12-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240827130814.732181-9-karol.kolacinski@intel.com> References: <20240827130814.732181-9-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org Instead of using shifts and casts, use FIELD_PREP after reading 40b timestamp values. Reviewed-by: Simon Horman Signed-off-by: Karol Kolacinski --- V5 -> V6: Replaced removed macros with the new ones drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 9 ++++++--- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 13 +++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 0fc4092fd261..65a66225797e 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1520,7 +1520,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -3199,7 +3200,8 @@ ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = FIELD_PREP(TS_PHY_HIGH_M, hi) | FIELD_PREP(TS_PHY_LOW_M, lo); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -4952,7 +4954,8 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) /* For E810 devices, the timestamp is reported with the lower 32 bits * in the low register, and the upper 8 bits in the high register. */ - *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); return 0; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 51bc691f1d0f..3968e064cc22 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -676,15 +676,12 @@ static inline bool ice_is_dual(struct ice_hw *hw) /* Source timer incval macros */ #define INCVAL_HIGH_M 0xFF -/* Timestamp block macros */ +/* PHY 40b registers macros */ +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) +#define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32) +#define PHY_40B_LOW_M GENMASK(7, 0) +#define PHY_40B_HIGH_M GENMASK_ULL(39, 8) #define TS_VALID BIT(0) -#define TS_LOW_M 0xFFFFFFFF -#define TS_HIGH_M 0xFF -#define TS_HIGH_S 32 - -#define TS_PHY_LOW_M 0xFF -#define TS_PHY_HIGH_M 0xFFFFFFFF -#define TS_PHY_HIGH_S 8 #define BYTES_PER_IDX_ADDR_L_U 8 #define BYTES_PER_IDX_ADDR_L 4