From patchwork Fri Aug 30 11:07:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 13784948 X-Patchwork-Delegate: kuba@kernel.org Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0D201A2868 for ; Fri, 30 Aug 2024 11:10:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725016249; cv=none; b=rEk3zeUWvHFdLDnPdidWlCkcxaAVSW9RiOX52Ifihlp//ru6Fm5u0vDCRSrVBYq3nE/0xYZYhS+ZJouiWnDCPercBDpcUTeGbKQ3WuWRES5t+Vve7Hz5lvQCl3KiahEFj5gxLKGd3HjZh4LTzdfvAcjIaEd1yHQLTHiBH13zxyU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725016249; c=relaxed/simple; bh=BtCbU89OhiBlJ5RhhRb0ndInbMuWIu+sg1jXIHjm/+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gi5urSBr+s7mZ8s8JLDIFIk8BIq1FFVI8ZHFnmOgW9/MCC49pB4dbvg69e/S2/7cfcCQUnLpg9sDU4+tEnf3NXugbe5ru0sHtqSZwcH/FIDPxn19rkVP9Wp3aDiN/wdpr5iemm5j64Iix7hvayMgrrSJhd55sXaBVassm07H+0s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Wmelv6EC; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Wmelv6EC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1725016248; x=1756552248; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BtCbU89OhiBlJ5RhhRb0ndInbMuWIu+sg1jXIHjm/+U=; b=Wmelv6ECamu18UioxpI1Qp9JozWob6ldL50WpJ2ec1B2Bxl2/qrQYUTg X1IneLIjndsK7Yqge06j7IjrWxVQrFOUG640GJXzyrWadrDQbBibjTuV8 Lcv8oyVxjehSrzgcjr2E6hive7yTri6D3QyXSA1emHz0UCFNbv2Lbi1Ig 9I1e10ow3A+KvVGsu8p7yFZAreqy2IRyIcfneXgJudRYn3zDNEKkmDc9/ VU/cjI3h9z7c5P8Q6Ar3mw8E8sftxk+AcHOKKXhZYobJNU2y8yOlPlXiI sfCUeyfVw5l3W/X8BuAp2yyHBAsZNfXwSEGQWIu+VQjPKx3FUBGK/K67s g==; X-CSE-ConnectionGUID: NBEZPVULRsyhVHmeQUpnDA== X-CSE-MsgGUID: 7BwxCZ2/SUCie3lXY/Z0nA== X-IronPort-AV: E=McAfee;i="6700,10204,11179"; a="23517601" X-IronPort-AV: E=Sophos;i="6.10,188,1719903600"; d="scan'208";a="23517601" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Aug 2024 04:10:48 -0700 X-CSE-ConnectionGUID: Kun/p8y+Ta+FYRymRXVQww== X-CSE-MsgGUID: ijQcXmCKR1ml2mA6zdH26A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,188,1719903600"; d="scan'208";a="68273651" Received: from kkolacin-desk1.igk.intel.com ([10.217.160.108]) by fmviesa005.fm.intel.com with ESMTP; 30 Aug 2024 04:10:45 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Cc: netdev@vger.kernel.org, anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com, Karol Kolacinski , Arkadiusz Kubalewski , Simon Horman Subject: [PATCH v4 iwl-next 5/7] ice: Disable shared pin on E810 on setfunc Date: Fri, 30 Aug 2024 13:07:21 +0200 Message-ID: <20240830111028.1112040-14-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20240830111028.1112040-9-karol.kolacinski@intel.com> References: <20240830111028.1112040-9-karol.kolacinski@intel.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Patchwork-Delegate: kuba@kernel.org When setting a new supported function for a pin on E810, disable other enabled pin that shares the same GPIO. Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Karol Kolacinski Reviewed-by: Simon Horman Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) --- V1 -> V2: Fixed incorrect call to ice_ptp_set_sma_cfg_e810t() drivers/net/ethernet/intel/ice/ice_ptp.c | 65 ++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 4d6f7efe18da..f733e673bf26 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -1838,6 +1838,63 @@ static void ice_ptp_enable_all_perout(struct ice_pf *pf) true); } +/** + * ice_ptp_disable_shared_pin - Disable enabled pin that shares GPIO + * @pf: Board private structure + * @pin: Pin index + * @func: Assigned function + * + * Return: 0 on success, negative error code otherwise + */ +static int ice_ptp_disable_shared_pin(struct ice_pf *pf, unsigned int pin, + enum ptp_pin_function func) +{ + unsigned int gpio_pin; + + switch (func) { + case PTP_PF_PEROUT: + gpio_pin = pf->ptp.ice_pin_desc[pin].gpio[1]; + break; + case PTP_PF_EXTTS: + gpio_pin = pf->ptp.ice_pin_desc[pin].gpio[0]; + break; + default: + return -EOPNOTSUPP; + } + + for (unsigned int i = 0; i < pf->ptp.info.n_pins; i++) { + struct ptp_pin_desc *pin_desc = &pf->ptp.pin_desc[i]; + unsigned int chan = pin_desc->chan; + + /* Skip pin idx from the request */ + if (i == pin) + continue; + + if (pin_desc->func == PTP_PF_PEROUT && + pf->ptp.ice_pin_desc[i].gpio[1] == gpio_pin) { + pf->ptp.perout_rqs[chan].period.sec = 0; + pf->ptp.perout_rqs[chan].period.nsec = 0; + pin_desc->func = PTP_PF_NONE; + pin_desc->chan = 0; + dev_dbg(ice_pf_to_dev(pf), "Disabling pin %u with shared output GPIO pin %u\n", + i, gpio_pin); + return ice_ptp_cfg_perout(pf, &pf->ptp.perout_rqs[chan], + false); + } else if (pf->ptp.pin_desc->func == PTP_PF_EXTTS && + pf->ptp.ice_pin_desc[i].gpio[0] == gpio_pin) { + pf->ptp.extts_rqs[chan].flags &= ~PTP_ENABLE_FEATURE; + pin_desc->func = PTP_PF_NONE; + pin_desc->chan = 0; + dev_dbg(ice_pf_to_dev(pf), "Disabling pin %u with shared input GPIO pin %u\n", + i, gpio_pin); + return ice_ptp_cfg_extts(pf, &pf->ptp.extts_rqs[chan], + false); + } + } + + return 0; +} + /** * ice_verify_pin - verify if pin supports requested pin function * @info: the driver's PTP info structure @@ -1872,6 +1929,14 @@ static int ice_verify_pin(struct ptp_clock_info *info, unsigned int pin, return -EOPNOTSUPP; } + /* On adapters with SMA_CTRL disable other pins that share same GPIO */ + if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) { + ice_ptp_disable_shared_pin(pf, pin, func); + pf->ptp.pin_desc[pin].func = func; + pf->ptp.pin_desc[pin].chan = chan; + return ice_ptp_set_sma_cfg(pf); + } + return 0; }