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Sat, 7 Sep 2024 03:19:24 -0500 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v3 04/20] cxl: move pci generic code Date: Sat, 7 Sep 2024 09:18:20 +0100 Message-ID: <20240907081836.5801-5-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> References: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017096:EE_|SJ1PR12MB6242:EE_ X-MS-Office365-Filtering-Correlation-Id: 43bd8324-dde3-4341-a7b2-08dccf15c9b0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: bMeMRUPQspkDvaOdU08H6f7T5bnheRzbdgp7uImCYcEi5i+/gJa0AXBE1bA2VNo6/geWLLet6+HZqXWt3fbXljilDjSwHwgQjkLbKBN8XiTyelBHl+MUo+tegG5YRk077jkGsmMIxVQo1nvHvYB9TRwzE/v1sGijGeaJnkrPb3Tdg4jfJWWXvE+1a/K6zFW10Dw1a9irV48Y9oR+uEc87z1G57NkYf9h6OE85gn7a4CEIKwc61W9ri7+53GT61a/4eJrG/oDtmLIEJSy8OCV7a4DpXGafLpfHhQBZsc/y612jdYh3ZZpSipyFc96uY3cJxQ3geB3gb0VFMslmlykXYg+NaqK4eL1ggeYOdeMftYpVA7cQ5CvgxRcGoQP3xP6rXH4u4StcMWfj17sPATe2FWm4FoO74fDVXYcz6z3sQeTiZoZQ2aLATmkN5E0/XG9/mHNiEtpJ6mjHQ2uvLvOUGyUfdjCLHNFxvB4Ds8b8WKGpcB+6dcubIs+bgtumPckZkccb4J5tC7ryy+K/USsNcjFlW1GY7J3112ic9JyleJilAw9Ag7w/ES6vjN/oU1NpMQq1nYV8MfUe+koLZwZvp3e8YSwXFe74znu0HhvpK3EJc/odG/mNTqtLTz55GRYUa0O1fDJmBnYyAMe+OT6p+NCTJMOpRDZKQ2KquVd7RxxSPDvCQXICo81k98tNi25RSoHd4URxeevhG6VHx4jUOMKgAa+GDbJ70iyJHo0L1NDz1pxd9T0uG4Kfcc5AoRrOvvawZsCHCBgbJb7pWtjrc3gHIrGpmromTYcLtUeCT7io10CUd70x6p6mm2u8DVA5bCSsW68imOwCNA93Pu5I1IgsO7Ak8FbwTAA/dEhe1fCdzieLjDTjt+Rmk6vdXNAhI3RAycb5GPi9Xv7RWeo0sUgl+pienAXgJ4zCcRevee9lD7zAtEwzfMZLVpYjIjMl0+ju3+W4v4J6I74Gv3vBz5lDD3SjFxkUV6x5gTKPyEoCLV/U5DEEtR5RYMvIQRL2TJuL9drfvUdzgqPjd07RwqPQHzFNTT2AwAauPKt8LzqT7b8UTy4sKrGqMSuyaOG8S8hJC0cWPx0bNfMj3xHXBNb/bOnlZRH1NP/SCHjyV3woFfA133YGQb+CxbNnE8zkpXX4PDYugx5+il5gbaMf76AN6c1GsPr5BWByAnzPuxnyTtckjvjKbS+SMxktgFhEfWZ3L+VSG/53KI8MWuE3hWdu/u/OqdIEpwtcD9DUNvd5qJrGFMGpj7B+u2CZyLqD11sMFMhGvLpjpfEWTIQ/c+gQIXxyMAGBYIzHzLGJl4aViVrmCuX1eHhMM7eRe/XzQ1rThSwwg0C1ANmb4+sAgz8nfVx2lKhozM9AB5FN5NUhBoLq7fdbVqvo3Uo3xvjHd6XEWPmLWj2xI+bKXJzmqeiGvDmEQ1pxiv4NTNGt9uxtoY73UgDSH0QTDHk2bBb X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2024 08:19:26.3578 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43bd8324-dde3-4341-a7b2-08dccf15c9b0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017096.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6242 From: Alejandro Lucero Inside cxl/core/pci.c there are helpers for CXL PCIe initialization meanwhile cxl/pci.c implements the functionality for a Type3 device initialization. Move those functions required also for Type2 initialization to cxl/core/pci.c with a specific function using that moved code added in a following patch. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 63 ++++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 ++ drivers/cxl/pci.c | 60 ---------------------------------------- 3 files changed, 66 insertions(+), 60 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 57370d9beb32..bf57f081ef8f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1079,6 +1079,69 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); +/* + * Assume that any RCIEP that emits the CXL memory expander class code + * is an RCD + */ +bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, CXL); + +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map) +{ + struct cxl_port *port; + struct cxl_dport *dport; + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + port = cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); + + put_device(&port->dev); + + if (component_reg_phys == CXL_RESOURCE_NONE) + return -ENXIO; + + map->resource = component_reg_phys; + map->reg_type = CXL_REGLOC_RBI_COMPONENT; + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; + + return 0; +} + +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, + u32 *caps) +{ + int rc; + + rc = cxl_find_regblock(pdev, type, map); + + /* + * If the Register Locator DVSEC does not exist, check if it + * is an RCH and try to extract the Component Registers from + * an RCRB. + */ + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) + rc = cxl_rcrb_get_comp_regs(pdev, map); + + if (rc) + return rc; + + return cxl_setup_regs(map, caps); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); + bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, u32 *current_caps) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index eb59019fe5f3..786b811effba 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +bool is_cxl_restricted(struct pci_dev *pdev); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, u32 *caps); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bec660357eec..2b85f87549c2 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -463,66 +463,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) return 0; } -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -static bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} - -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, - struct cxl_register_map *map) -{ - struct cxl_port *port; - struct cxl_dport *dport; - resource_size_t component_reg_phys; - - *map = (struct cxl_register_map) { - .host = &pdev->dev, - .resource = CXL_RESOURCE_NONE, - }; - - port = cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); - - put_device(&port->dev); - - if (component_reg_phys == CXL_RESOURCE_NONE) - return -ENXIO; - - map->resource = component_reg_phys; - map->reg_type = CXL_REGLOC_RBI_COMPONENT; - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; - - return 0; -} - -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, - struct cxl_register_map *map, u32 *caps) -{ - int rc; - - rc = cxl_find_regblock(pdev, type, map); - - /* - * If the Register Locator DVSEC does not exist, check if it - * is an RCH and try to extract the Component Registers from - * an RCRB. - */ - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) - rc = cxl_rcrb_get_comp_regs(pdev, map); - - if (rc) - return rc; - - return cxl_setup_regs(map, caps); -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);