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Mon, 23 Sep 2024 06:45:45 -0700 From: Paritosh Dixit To: Alexandre Torgue , Jose Abreu , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , "Thierry Reding" , Jonathan Hunter CC: Bhadram Varka , Revanth Kumar Uppala , , , Paritosh Dixit Subject: [PATCH] net: stmmac: dwmac-tegra: Fix link bring-up sequence Date: Mon, 23 Sep 2024 09:44:10 -0400 Message-ID: <20240923134410.2111640-1-paritoshd@nvidia.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3C:EE_|PH7PR12MB7870:EE_ X-MS-Office365-Filtering-Correlation-Id: e9c9af50-6247-48dd-99e4-08dcdbd61427 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: czewiuhlytgsDMu8verhlX/TwN/IiR+ihvLlAojrNblCjptbOjfben4LxhYruox2Apm36ZH2mZq6eeGPfCRvNWCJ27pIga4C9Ki221n35HjeqiCJCa+yThhGHiXYJUtFjJDiBZBBipGKJvVT9rx234maoXP1Ryt9mAZ53GQEzAoDY28TrBrIAMIw/gfHX08V3QpAGKpuo0jzjtwJDxERFR5fBXHKk7jaDlRZIt68FNViCN6cTwGs6paJCitfNQZ06X8Xq0h41UILUKIeaF/GUuZMs7navcEIxHJ7QtEDgAtg8iFAAU48K+slAKcSwPbf/uRvWH7afl/XfdEGaRcSSbLmM2pJa2QVsYVJ2L+Rl9yMPJGCxcaEPXLwSEh0DvuaLzvwLsoSDbgZzi5FPZgrhXhWnU146rVwu9kZd6+yx0CYDboS4rx0bf1FFibbWfYTVrSkV1uA+S9eZJZy5IGHRCEIXtR/ySb4tU4M/+gqipS4KBI7tIMFoAyHVoPqMwWJRX5lO3EWvPJ35i1HeVxLgATp5VEf1JQbXsfeW7TPakEQRgQ1elClE2ymNncfOccxnsHR4VkN9GHNeBH9MxtHilu/IUngFUpXnXVaDDxl0aTCkzmKyTTk50Pl8wEkFUuvgTdQfOddz+0d0j+CyZn9LdDM1YBYoA0K0GhpjiGmcLEFl/EdFesfy2mbF22nrjJ1SwJgN3mqDDaGS9l+qVS0LpwBH+Yfi+lV9VkjWY9PXcf08LKdkxqmfnT6+GtklrGkrbHYmdunjMPzQKitTuGBxRXWkp4ys9781XKNqQGwG3Lnduo97DNFcpWBkHQeXnGI07njPtirF7sY2E8U5FQvLccqGsC2YCmJzOqbzG9aaE5ULvyVRBHkZH5Dlccny3D6GiC7kipD15sBI80wS5oeJ/2B5Pxl3/hOyhyoULI6mSo/6JOw4gcKaLeR9O2MvapH3l9CXlYXhFDsaSqitiW9mznsXRcOOQYAV44e/R8S344DrdyBbjY3XLXwqgQmVyPWr2mldtRUFKHxSow8gVCsTHroD5ASzX7IPFUSmy6mNaaOfPXc8Fkfv9KAJT/7gDpq8uQwxUAMPRFfZQ3XmdRYdklGjpnR0AokCYBOQP6GyUr1kF7GYjAJVztPN9G8FrsR+AgxF8EVtrM+Mk0X7eyIptLCnYgiGNvcCTtqddfxXkAuhxp9pX8STn9BkF+SmwUmsnkk+PaA+F1zROni9rzJbZGixNvOSu2UH1TUB3QmDdZLHLO0Us7qaXnZ8i+lVeAUQJNWX1ALM0H/aGnV7lRmjoHXtmFoxPsQLxo7lwymwUA87pbwSu8sFLOR2uhlz9lhXpXSwJ1Ra1C3E0Ej0QBGKZwNB77M/7SBYIk38qThSHpDIJP2taClzZrXi6tT8sH5RkWAFKgbNCQvQ6G/RV6PmJwKD3QpQgIFfGm+Vzy732a4kn4LLd/qIQLGzzCWyTlr X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2024 13:46:08.6297 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e9c9af50-6247-48dd-99e4-08dcdbd61427 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7870 X-Patchwork-Delegate: kuba@kernel.org The Tegra MGBE driver sometimes fails to initialize, reporting the following error, and as a result, it is unable to acquire an IP address with DHCP: tegra-mgbe 6800000.ethernet: timeout waiting for link to become ready As per the recommendation from the Tegra hardware design team, fix this issue by: - clearing the PHY_RDY bit before setting the CDR_RESET bit and then setting PHY_RDY bit before clearing CDR_RESET bit. This ensures valid data is present at UPHY RX inputs before starting the CDR lock. - adding the required delays when bringing up the UPHY lane. Note we need to use delays here because there is no alternative, such as polling, for these cases. Without this change we would see link failures on boot sometimes as often as 1 in 5 boots. With this fix we have not observed any failures in over 1000 boots. Fixes: d8ca113724e7 ("net: stmmac: tegra: Add MGBE support") Signed-off-by: Paritosh Dixit Reviewed-by: Jon Hunter Tested-by: Jon Hunter --- drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c index 362f85136c3e..c81ae5f8fef4 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c @@ -127,10 +127,12 @@ static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_ value &= ~XPCS_WRAP_UPHY_RX_CONTROL_AUX_RX_IDDQ; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + ndelay(50); // 50ns min delay needed as per HW design value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_SLEEP; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + ndelay(500); // 500ns min delay needed as per HW design value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CAL_EN; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); @@ -143,22 +145,30 @@ static int mgbe_uphy_lane_bringup_serdes_up(struct net_device *ndev, void *mgbe_ return err; } + ndelay(50); // 50ns min delay needed as per HW design value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_DATA_EN; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); - value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + ndelay(50); // 50ns min delay needed as per HW design value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); - value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + ndelay(50); // 50ns min delay needed as per HW design value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); value |= XPCS_WRAP_UPHY_RX_CONTROL_RX_PCS_PHY_RDY; writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + msleep(30); // 30ms delay needed as per HW design + value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + value &= ~XPCS_WRAP_UPHY_RX_CONTROL_RX_CDR_RESET; + writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); + err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, value & XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS, 500, 500 * 2000);