| Message ID | 20240929101949.723658-5-me@shenghaoyang.info (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | net: dsa: mv88e6xxx: fix MV88E6393X PHC frequency on internal clock | expand |
Hi Shenghao, kernel test robot noticed the following build warnings: [auto build test WARNING on net/main] url: https://github.com/intel-lab-lkp/linux/commits/Shenghao-Yang/net-dsa-mv88e6xxx-group-cycle-counter-coefficients/20240929-182245 base: net/main patch link: https://lore.kernel.org/r/20240929101949.723658-5-me%40shenghaoyang.info patch subject: [PATCH net 3/3] net: dsa: mv88e6xxx: support 4000ps cycle counter period config: sparc64-randconfig-r133-20240930 (https://download.01.org/0day-ci/archive/20241001/202410011454.X1kiOgOz-lkp@intel.com/config) compiler: sparc64-linux-gcc (GCC) 14.1.0 reproduce: (https://download.01.org/0day-ci/archive/20241001/202410011454.X1kiOgOz-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410011454.X1kiOgOz-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) drivers/net/dsa/mv88e6xxx/ptp.c:35:34: sparse: sparse: symbol 'mv88e6xxx_cc_10ns_coeffs' was not declared. Should it be static? drivers/net/dsa/mv88e6xxx/ptp.c:49:34: sparse: sparse: symbol 'mv88e6xxx_cc_8ns_coeffs' was not declared. Should it be static? >> drivers/net/dsa/mv88e6xxx/ptp.c:63:34: sparse: sparse: symbol 'mv88e6xxx_cc_4ns_coeffs' was not declared. Should it be static? vim +/mv88e6xxx_cc_4ns_coeffs +63 drivers/net/dsa/mv88e6xxx/ptp.c 55 56 /* Family MV88E6393X using internal clock: 57 * Raw timestamps are in units of 4-ns clock periods. 58 * 59 * clkadj = scaled_ppm * 4*2^28 / (10^6 * 2^16) 60 * simplifies to 61 * clkadj = scaled_ppm * 2^8 / 5^6 62 */ > 63 const struct mv88e6xxx_cc_coeffs mv88e6xxx_cc_4ns_coeffs = { 64 .cc_shift = 28, 65 .cc_mult = 4 << 28, 66 .cc_mult_num = 1 << 8, 67 .cc_mult_dem = 15625ULL 68 }; 69
diff --git a/drivers/net/dsa/mv88e6xxx/ptp.c b/drivers/net/dsa/mv88e6xxx/ptp.c index be1fcbf75440..6a88895845ea 100644 --- a/drivers/net/dsa/mv88e6xxx/ptp.c +++ b/drivers/net/dsa/mv88e6xxx/ptp.c @@ -39,7 +39,7 @@ const struct mv88e6xxx_cc_coeffs mv88e6xxx_cc_10ns_coeffs = { .cc_mult_dem = 3125ULL, }; -/* Other families: +/* Other families except MV88E6393X in internal clock mode: * Raw timestamps are in units of 8-ns clock periods. * * clkadj = scaled_ppm * 8*2^28 / (10^6 * 2^16) @@ -53,6 +53,20 @@ const struct mv88e6xxx_cc_coeffs mv88e6xxx_cc_8ns_coeffs = { .cc_mult_dem = 15625ULL }; +/* Family MV88E6393X using internal clock: + * Raw timestamps are in units of 4-ns clock periods. + * + * clkadj = scaled_ppm * 4*2^28 / (10^6 * 2^16) + * simplifies to + * clkadj = scaled_ppm * 2^8 / 5^6 + */ +const struct mv88e6xxx_cc_coeffs mv88e6xxx_cc_4ns_coeffs = { + .cc_shift = 28, + .cc_mult = 4 << 28, + .cc_mult_num = 1 << 8, + .cc_mult_dem = 15625ULL +}; + #define TAI_EVENT_WORK_INTERVAL msecs_to_jiffies(100) #define cc_to_chip(cc) container_of(cc, struct mv88e6xxx_chip, tstamp_cc) @@ -107,6 +121,8 @@ mv88e6xxx_cc_coeff_get(struct mv88e6xxx_chip *chip) } switch (period_ps) { + case 4000: + return &mv88e6xxx_cc_4ns_coeffs; case 8000: return &mv88e6xxx_cc_8ns_coeffs; case 10000: @@ -484,10 +500,10 @@ static u64 mv88e6xxx_ptp_clock_read(const struct cyclecounter *cc) return 0; } -/* With a 125MHz input clock, the 32-bit timestamp counter overflows in ~34.3 +/* With a 250MHz input clock, the 32-bit timestamp counter overflows in ~17.2 * seconds; this task forces periodic reads so that we don't miss any. */ -#define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 16) +#define MV88E6XXX_TAI_OVERFLOW_PERIOD (HZ * 8) static void mv88e6xxx_ptp_overflow_check(struct work_struct *work) { struct delayed_work *dw = to_delayed_work(work);
The MV88E6393X family of devices can run its cycle counter off an internal 250MHz clock instead of an external 125MHz one. Add support for this cycle counter period by adding another set of coefficients and lowering the periodic cycle counter read interval to compensate for faster overflows at the increased frequency. Otherwise, the PHC runs at 2x real time in userspace and cannot be synchronized. Fixes: de776d0d316f ("net: dsa: mv88e6xxx: add support for mv88e6393x family") Signed-off-by: Shenghao Yang <me@shenghaoyang.info> --- drivers/net/dsa/mv88e6xxx/ptp.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-)