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Wed, 9 Oct 2024 00:40:07 -0500 From: Vineeth Karumanchi To: , , , , , , , , , , CC: , , , , Subject: [RFC PATCH net-next 4/5] net: macb: Configure High Speed Mac for given speed. Date: Wed, 9 Oct 2024 11:09:45 +0530 Message-ID: <20241009053946.3198805-5-vineeth.karumanchi@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241009053946.3198805-1-vineeth.karumanchi@amd.com> References: <20241009053946.3198805-1-vineeth.karumanchi@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002325:EE_|CH3PR12MB7739:EE_ X-MS-Office365-Filtering-Correlation-Id: 68d0c577-ee81-4e66-6dcd-08dce824d91f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|36860700013|82310400026|921020; X-Microsoft-Antispam-Message-Info: w3ud4zo9WP19Ay8W+Hb7Mi74Kyyl/0iqC44MblYnrAWlFKXAvFVpOuNAxhdDSxD0EGkvK3DM/MWh5LVSzZ09DYnzkzSLUeRNu3gbtFymuMldpEeIAVg2AzUpElzfyPnpc8EyepzHs/8jfPhNSiCSAoYCpi2+9zufsaCgyJH8DDfw4FodU8g79oFlG5NgwRlhqYbfp/pI8rC8Yl2iuJSVQDcfOGymoTdnlak/cxGsskHZ1pT8gs/GE/XMoe1eycCqcEsBwx1sxUWu6vVtAzQYcRqz+zDBXI5RNqvgsABt0gDB7Xa155s0KKIvVtKfzDRnYcQXGj/9+v3T9v9deHA+d8SYYjm/JVgRNR+IjtZ02LsIv2NLxI3TMivJjm+OnAK16Xvdij2FaBzBFBeu39IQWJ/3/FAEfkKZThrNiYKZh4xI37lXipbZv652BAmZLSqugd4+KaHod1u6SXFmz9VHOiN+am5glC/aEKnAEuFxHGVn2r1uNQ9QIcW08TDNYY6xblJp4w2N+pfrZB0BYuo7ZsOHKfKNvncaNZVFLkvgwA03WhyIzxECE2ZIlRFzX1AUMEAoLP8yleqoGlyT/g6lWkV441ynOT2CaOClNcm39WidzBB1teo30qV6FT4JnYSK6JEoxTfPdFpXpiPPeO5Flr20k8Z/anhp9JFy9BPOl5rQMOR752UL/vvJa+zqpVG3xOY2XAWCmWd75YtzsOzaBqwmWMaigXEDnt9bvWncp2SnKyQd0lwp+p1YyxG+6NkKYiHYfXAFnffwcCMld5MSCVPw3QLMVP9QB4owvi1GoU7jpzBFoHA76RtSIGXoSmGBEDRDCqlVIVE9ZoWaG3kI7MXEIHIb1amkTKr6XcDuT5UEg5RkW1Q38xUxViEo6MmVdlzZTT1qlR8GzOJMpaOx/UtWZr9yWWETeqq/lKDQKjVZDJVGgQxsW7cVigUlYD/prjgMKVV9qU2DsX+80X5BjQBSEDt3I+USTyIHsbQvg15EkjPz1KSKey4/LPduqSoxmxdd7HZkeAgOQVn030++ZVk3hn9IRG4uRTXVWtvjguozKCu4uayHDR2et+otzlkArkAyRKL/ZvxvTw6jKgWqZlA3n2wtqfmuhhLbtoopRSeUVfQqRkh8dd0TWwpg8DkVtwC02fztlAUQ1veSX1WX6+jWVmllSBN2Kiw6kwaxkPY93+S28q03dNwDytpS1QuNTdC2IWBfM44ntJ8gkSy0WpnYBoSQYOJp3WgZbDPJQsPj1sFhIY7C/VjUVfewK6xtnBZWBdxlj8AoT6OH5yy6KpNC3QO/DgHKa28s+rP4m0YNL7Qtm66oxIMHYOmVaYkWP5AZovGz6KIVQaWpmSVaeSrUhKkHyXzxbyoy2Xfoi7jCJup7eDkmmtHKo7JmYyz7 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(36860700013)(82310400026)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 05:40:13.7543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68d0c577-ee81-4e66-6dcd-08dce824d91f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002325.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB7739 X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC HS Mac configuration steps: - Configure speed and serdes rate bits of USX_CONTROL register from user specified speed in the device-tree. - Enable HS Mac for 5G and 10G speeds. - Reset RX receive path to achieve USX block lock for the configured serdes rate. - Wait for USX block lock synchronization. Move the initialization instances to macb_usx_pcs_link_up(). Signed-off-by: Vineeth Karumanchi --- drivers/net/ethernet/cadence/macb.h | 1 + drivers/net/ethernet/cadence/macb_main.c | 57 ++++++++++++++++++++---- 2 files changed, 50 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 47e80fa72865..ed4edeac3a59 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -825,6 +825,7 @@ }) #define MACB_READ_NSR(bp) macb_readl(bp, NSR) +#define MACB_READ_USX_STATUS(bp) gem_readl(bp, USX_STATUS) /* struct macb_dma_desc - Hardware DMA descriptor * @addr: DMA address of data buffer diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 3f9dc0b037c0..7beb775a0bd7 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -94,6 +94,7 @@ struct sifive_fu540_macb_mgmt { #define MACB_PM_TIMEOUT 100 /* ms */ #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */ +#define GEM_SYNC_TIMEOUT 2500000 /* in usecs */ /* DMA buffer descriptor might be different size * depends on hardware configuration: @@ -564,14 +565,59 @@ static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode, int duplex) { struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs); - u32 config; + u32 speed_val, serdes_rate, config; + bool hs_mac = false; + + switch (speed) { + case SPEED_1000: + speed_val = HS_SPEED_1000M; + serdes_rate = MACB_SERDES_RATE_1G; + break; + case SPEED_2500: + speed_val = HS_SPEED_2500M; + serdes_rate = MACB_SERDES_RATE_2_5G; + break; + case SPEED_5000: + speed_val = HS_SPEED_5000M; + serdes_rate = MACB_SERDES_RATE_5G; + hs_mac = true; + break; + case SPEED_10000: + speed_val = HS_SPEED_10000M; + serdes_rate = MACB_SERDES_RATE_10G; + hs_mac = true; + break; + default: + netdev_err(bp->dev, "Specified speed not supported\n"); + return; + } + + /* Enable HS MAC for high speeds */ + if (hs_mac) { + config = macb_or_gem_readl(bp, NCR); + config |= GEM_BIT(ENABLE_HS_MAC); + macb_or_gem_writel(bp, NCR, config); + } + + /* Configure HS MAC for specified speed */ + config = gem_readl(bp, HS_MAC_CONFIG); + config = GEM_BFINS(HS_MAC_SPEED, speed_val, config); + gem_writel(bp, HS_MAC_CONFIG, config); config = gem_readl(bp, USX_CONTROL); - config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config); - config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config); + config = GEM_BFINS(SERDES_RATE, serdes_rate, config); + config = GEM_BFINS(USX_CTRL_SPEED, speed_val, config); config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS)); + config |= GEM_BIT(RX_SYNC_RESET); + gem_writel(bp, USX_CONTROL, config); + mdelay(250); + config &= ~GEM_BIT(RX_SYNC_RESET); config |= GEM_BIT(TX_EN); gem_writel(bp, USX_CONTROL, config); + + if (readx_poll_timeout(MACB_READ_USX_STATUS, bp, config, config & GEM_BIT(USX_BLOCK_LOCK), + 1, GEM_SYNC_TIMEOUT)) + netdev_err(bp->dev, "USX PCS block lock not achieved\n"); } static void macb_usx_pcs_get_state(struct phylink_pcs *pcs, @@ -662,7 +708,6 @@ static void macb_mac_config(struct phylink_config *config, unsigned int mode, ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL); } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) { ctrl |= GEM_BIT(PCSSEL); - ncr |= GEM_BIT(ENABLE_HS_MAC); } else if (bp->caps & MACB_CAPS_MIIONRGMII && bp->phy_interface == PHY_INTERFACE_MODE_MII) { ncr |= MACB_BIT(MIIONRGMII); @@ -766,10 +811,6 @@ static void macb_mac_link_up(struct phylink_config *config, macb_or_gem_writel(bp, NCFGR, ctrl); - if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER) - gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M, - gem_readl(bp, HS_MAC_CONFIG))); - spin_unlock_irqrestore(&bp->lock, flags); if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))