From patchwork Thu Oct 10 06:16:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Herve Codina X-Patchwork-Id: 13829540 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFE4F1BBBC0; Thu, 10 Oct 2024 06:16:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.196 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728540993; cv=none; b=IdOkcRAtWvQvB0kfyg5rhH5mKGswOhU/GvDUlsXidhrBFMajqBGAg6uOCMJ+hj3hDyxvxr7+/CDM9tcp2QiIlo2WYfv3M6Y/mvYtwYbB+Q1f1VNNVrZufacAJlgufnkp3JumMtR8La1kKnk043S7fMM8y6m9FBpZ0/oTQM3Ev0k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728540993; c=relaxed/simple; bh=zOwm1cxscEGCjNLHPiQEn5PI7KQsbTev9ncSYRPwirA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AI8vIhVz9a6pD/V3C9Z1me5JYcW3bC5Vq79qULBA9/LmM4oK0WOqpmZ6muudF18i+fghcxH9k8Q6acd8Bb2FoC1287RZh2lQU2tZpuoRD3lA1Ko51Yzz2ezv0RRHRrcAiA+0QkiGUe7ggVT2tiUeMVyfV0SXu6Ag6pr/Mb36uuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Jp1bCegg; arc=none smtp.client-ip=217.70.183.196 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Jp1bCegg" Received: by mail.gandi.net (Postfix) with ESMTPA id D0B1FE000E; Thu, 10 Oct 2024 06:16:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1728540989; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EOckyBBlTDDnkyo3cyvGWjnrUpORqQ7Zmtbq/7BIU3A=; b=Jp1bCegg8QC2uRHpYTP57pzql+JaomweDkcTCHe5AHiZTYpwEm+JM1FgDbtZeQV+swTmRw sqCxHBudDN/jA+XA/GXzMGankPusf7XJfjLogUo7/oIPmrLYOAIz8IakniCh5bgCY4Uthq RP+zLKlOPglrpp1ODcUm5kKnZuqTJk+nQS48AXoke+o9gBS4pFwr12AiuoI8U3d3mlYwM6 ssL7pNBfE5c5X4QL4Wbzq0D8ElmAg/PBvb93dxEg5cg+8Ovz/EnpsQdQXlAAMJ9vSX70f7 f2ZnzGH3xl4W5LrT7jyC2utVhKxDOYVlXGVzIQEFcysHFeZUZDK9zmMnR4XbRw== From: Herve Codina To: Geert Uytterhoeven , Andy Shevchenko , Simon Horman , Lee Jones , Arnd Bergmann , Derek Kiernan , Dragan Cvetic , Greg Kroah-Hartman , Herve Codina , Bjorn Helgaas , Philipp Zabel , Lars Povlsen , Steen Hegelund , Daniel Machon , UNGLinuxDriver@microchip.com, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Saravana Kannan Cc: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Horatiu Vultur , Andrew Lunn , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Allan Nielsen , Steen Hegelund , Luca Ceresoli , Thomas Petazzoni , =?utf-8?b?Q2zDqW1lbnQgTMOp?= =?utf-8?b?Z2Vy?= Subject: [PATCH v8 5/6] reset: mchp: sparx5: Allow building as a module Date: Thu, 10 Oct 2024 08:16:13 +0200 Message-ID: <20241010061615.787073-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241010061615.787073-1-herve.codina@bootlin.com> References: <20241010061615.787073-1-herve.codina@bootlin.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: herve.codina@bootlin.com From: Clément Léger This reset controller can be used by the LAN966x PCI device. The LAN966x PCI device driver can be built as a module and this reset controller driver has no reason to be a builtin driver in that case. Signed-off-by: Clément Léger Signed-off-by: Herve Codina Reviewed-by: Steen Hegelund --- drivers/reset/Kconfig | 2 +- drivers/reset/reset-microchip-sparx5.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 86a5504950cb..93cddbe8609b 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -146,7 +146,7 @@ config RESET_LPC18XX This enables the reset controller driver for NXP LPC18xx/43xx SoCs. config RESET_MCHP_SPARX5 - bool "Microchip Sparx5 reset driver" + tristate "Microchip Sparx5 reset driver" depends on ARCH_SPARX5 || SOC_LAN966 || MCHP_LAN966X_PCI || COMPILE_TEST default y if SPARX5_SWITCH select MFD_SYSCON diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c index 48a62d5da78d..c4cc0edbb250 100644 --- a/drivers/reset/reset-microchip-sparx5.c +++ b/drivers/reset/reset-microchip-sparx5.c @@ -191,6 +191,7 @@ static const struct of_device_id mchp_sparx5_reset_of_match[] = { }, { } }; +MODULE_DEVICE_TABLE(of, mchp_sparx5_reset_of_match); static struct platform_driver mchp_sparx5_reset_driver = { .probe = mchp_sparx5_reset_probe, @@ -213,3 +214,4 @@ postcore_initcall(mchp_sparx5_reset_init); MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver"); MODULE_AUTHOR("Steen Hegelund "); +MODULE_LICENSE("GPL");