| Message ID | 20241010150543.2620448-1-s-vadapalli@ti.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next] net: ethernet: ti: am65-cpsw: Enable USXGMII mode for J7200 CPSW5G | expand |
On 10/10/2024 18:05, Siddharth Vadapalli wrote: > TI's J7200 SoC supports USXGMII mode. Add USXGMII mode to the > extra_modes member of the J7200 SoC data. > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org>
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c index 12ccdd3f19aa..09e57e66ea48 100644 --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c @@ -3445,7 +3445,8 @@ static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { .quirks = 0, .ale_dev_id = "am64-cpswxg", .fdqring_mode = K3_RINGACC_RING_MODE_RING, - .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), + .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | + BIT(PHY_INTERFACE_MODE_USXGMII), }; static const struct am65_cpsw_pdata j721e_cpswxg_pdata = {
TI's J7200 SoC supports USXGMII mode. Add USXGMII mode to the extra_modes member of the J7200 SoC data. Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> --- Hello, This patch is based on commit 16aef66643a2 net: phy: Validate PHY LED OPs presence before registering of the "main" branch of the net-next tree. Regards, Siddharth. drivers/net/ethernet/ti/am65-cpsw-nuss.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)