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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , , Tariq Toukan Subject: [PATCH net-next V2 04/15] net/mlx5: Restrict domain list insertion to root TSAR ancestors Date: Mon, 14 Oct 2024 23:52:49 +0300 Message-ID: <20241014205300.193519-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241014205300.193519-1-tariqt@nvidia.com> References: <20241014205300.193519-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE2:EE_|DS0PR12MB9422:EE_ X-MS-Office365-Filtering-Correlation-Id: 5daf1027-9f9c-4b7d-898d-08dcec926360 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: brat3whFHg0zlFc0fmnP20gMrtOia0kw+wPkGtrH4bk3VIxmmPq657D3QV0ifXghtRfWuAup8IABPd6WRkBCjBZAmkc18B/+y7m+cr18rGfS51q6vy6GMeXyjNaUfpEcPhvLOGkO9S/uSSnJZUQ3ei8o4aQSeIM4snVcHi57GN8jCgfYrju3ifTCshVpiCVZ+/HWSvlnYT5KysPqmmruItWj+aPOzMqDNzft1DbVsjIqMzHCEJVTn+Gh5YgfHQ6OqcnFrCsjX7sy/V+J/NgvZ9iy4XALbGe4PdxwIrnGCnb1WaHSdjDQeeI6DS/2SoZAV9SnBvApJkP9RvaB7aNMfenb720/nidussZnNQpoZElbGtPFsq8wroL3Bzdot3+A9VtPBpgNEM9wlaDvuVQwUErIpKZ1yZ2EEFMTp7/nZ6lnVQ6/uVidWMNLkfniFKXfxzDMIru7/ggMNf3qPy89FY2YWpjZNrddJUnbaG8GCgL9gIZmI6eFX5r4kvNlSJ8TF4es4GM8Cm2mMlpwDDvJOTc5CaQ77Z2uf037zOC76pSqDVO9GweOhkMcWIAeb6cE3BJBqMoeYy51Di6ZqtHURDO0AzlyqptJCsdWr/kf1lQA+JQQcoq4nHZkDMc643s9sXGDC10HGFzvKg200CbX/YNO5OoHuWsZvI3Qag+vxU6+DIJAlVCyCdKxISFnarzAWb5gkAp/PVfCgL2VNNOp7bibfGPo46fVAuau1i40xwrRKcPS7t0xroKVJST5NFpy74Zx3pKCXoNwsp3If9kqvA9qpkKp+/0lTr2blSzsdpTb5fXkwx3Z88WmFeghA6bPA4HTZbl3CfSeZYwFw1thxxcuqdFT8UDNlFFGyZ+wWRA4aDerp/MuwFnhibgRPYv+N4rYfcGRNU2SK+3zVrMWCHqQmsSrf8+yGebolkK9dnLyTaMsGRnY4d3Vu6qjHvWWFfQlyLQ2GMwC2ztZwNo8iBSqzdLw3PrCTGRyCdw8yL6hQI711pQ5td24TV9+4Z75dmTz3M5tDuT1k177FhOiGf+xEr53Yub8hxW0u8yM1M03fUwy5/378PfBKayv1nNMZoLrWcZFC1uTpI6Vf7T9ar2GUdpqrynp8gwalIbl8Lbdf7susQhWtNrXac/m/OB6gdY4cKhwGt3nHcrtgWJZPBd+prsIX0SIbjZ0uziBVhS3nrzhrAq22JW3wcGww4idx1dgsA4H59AHwyAeKITJurKVpNOVZZprxj0pqsKB1Rs6HuYUXL/KCdCMKzrxviOcelXQQOjQ0xhtt9z5F1cN36kKpNFUxOY+R2c96RRqxWU3cRAeBts2WBT8b4Nz9MWoImmbNbrSDcEYfpOCOWQe6vUMJNqH/XWn08RoZn/0ABY= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Oct 2024 20:54:25.5325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5daf1027-9f9c-4b7d-898d-08dcec926360 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9422 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Update the logic for adding rate groups to the E-Switch domain list, ensuring only groups with the root Transmit Scheduling Arbiter as their parent are included. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index f2a0d59fa5bb..dd6fe729f456 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -511,6 +511,7 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod struct mlx5_esw_rate_group *parent) { struct mlx5_esw_rate_group *group; + struct list_head *parent_list; group = kzalloc(sizeof(*group), GFP_KERNEL); if (!group) @@ -521,7 +522,9 @@ __esw_qos_alloc_rate_group(struct mlx5_eswitch *esw, u32 tsar_ix, enum sched_nod group->type = type; group->parent = parent; INIT_LIST_HEAD(&group->members); - list_add_tail(&group->parent_entry, &esw->qos.domain->groups); + parent_list = parent ? &parent->members : &esw->qos.domain->groups; + list_add_tail(&group->parent_entry, parent_list); + return group; }