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For example, num_tx_rings is 8 and bdr_int_num is 3. According to the previous logic, this results in two tx_bdr corresponding memories not being allocated, so when sending packets to tx ring 6 or 7, wild pointers will be accessed. Of course, this issue doesn't exist on LS1028A, because its num_tx_rings is 8, and bdr_int_num is either 1 or 2. However, there is a risk for the upcoming i.MX95. Therefore, it is necessary to ensure that each tx_bdr can be allocated to the corresponding memory. Signed-off-by: Clark Wang Signed-off-by: Wei Fang Reviewed-by: Claudiu Manoil Reviewed-by: Frank Li --- v2 changes: This patch is separated from v1 patch 9 ("net: enetc: optimize the allocation of tx_bdr"). Only the optimized part is kept. v3: no changes, just rebase the patch from the previous one. v4: no changes --- drivers/net/ethernet/freescale/enetc/enetc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c index bd725561b8a2..bccbeb1f355c 100644 --- a/drivers/net/ethernet/freescale/enetc/enetc.c +++ b/drivers/net/ethernet/freescale/enetc/enetc.c @@ -3049,10 +3049,10 @@ static void enetc_int_vector_destroy(struct enetc_ndev_priv *priv, int i) int enetc_alloc_msix(struct enetc_ndev_priv *priv) { struct pci_dev *pdev = priv->si->pdev; + int v_tx_rings, v_remainder; int num_stack_tx_queues; int first_xdp_tx_ring; int i, n, err, nvec; - int v_tx_rings; nvec = ENETC_BDR_INT_BASE_IDX + priv->bdr_int_num; /* allocate MSIX for both messaging and Rx/Tx interrupts */ @@ -3066,9 +3066,12 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv) /* # of tx rings per int vector */ v_tx_rings = priv->num_tx_rings / priv->bdr_int_num; + v_remainder = priv->num_tx_rings % priv->bdr_int_num; for (i = 0; i < priv->bdr_int_num; i++) { - err = enetc_int_vector_init(priv, i, v_tx_rings); + int num_tx_rings = i < v_remainder ? v_tx_rings + 1 : v_tx_rings; + + err = enetc_int_vector_init(priv, i, num_tx_rings); if (err) goto fail; }