From patchwork Wed Oct 23 22:01:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Machon X-Patchwork-Id: 13848009 X-Patchwork-Delegate: kuba@kernel.org Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5242A1D041B; Wed, 23 Oct 2024 22:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720928; cv=none; b=f+dqQ2rZ83SmzyMXRUKjU6Q6IxzoBwdlMt6TS2kF3rsGWLWwCLKpjGLRkc0DHdCeH4kwvdKEPZr2r6cB/MPX6xqD6JP5Ibx7tRbN+ZZq2KXStmcbwPmrI33FWOgS3yj8EU68fD1fBWEqPdfM4bNfpwvTFOE4Iitznw7hCVx4xi0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729720928; c=relaxed/simple; bh=Db4mo36NIk5280MwSTl+F0lyO0vOeJdT0JiFPqacJdE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=nj+t7gP8gdDCqLCpAlFKrQngxrrn+8/HowbIPfpKtWr32sNveWRWi/tSUyV0q61bOeZSx40QctVB5uRo7ePeSFhH9uluMP1d7v0rRyg3yXsuCOFiXkKVmQ0hZa3L+7MB6w41/WsMczvNxTPvHL0PO5KTOH6lJzeF4jR/0cR6LrY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=DmTHR4gT; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="DmTHR4gT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1729720926; x=1761256926; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=Db4mo36NIk5280MwSTl+F0lyO0vOeJdT0JiFPqacJdE=; b=DmTHR4gTEi1vljWZ2vITIUpKBRlzyrD3wK+0B1JbLDoNDvGJDIgKsZNp WdOkFratLt0OCjZ6VRZsLBvMWpZ4S3aam7ImY6EKi2qu8hhfPdZvxH8IY XStT0iR//kiGrdFf8k0Vxj33haUcX7bIjpFnbziRRPBgGLI/Hxe5BOhLh yF+uboxOjXCA7PZwesO3ZzqPreBRx5/EpSIlseyRsdO0GWf6PwWmiL7mN ijel9/XIoeSB/hBArRUusIrezHoRzMh+LAVJTDn2rF1/AFS0DKoT1q8QB KJHbPlpeEJUfhxpibR6rcCGUFkF1hv0gu3CC0qu70NIpEofb176s8Qv7B A==; X-CSE-ConnectionGUID: 1Xapdzk8QAqz3uJYdYtrIg== X-CSE-MsgGUID: wZ/VQMLxRG6JieyzTeqSLA== X-IronPort-AV: E=Sophos;i="6.11,227,1725346800"; d="scan'208";a="33409630" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 23 Oct 2024 15:02:04 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 23 Oct 2024 15:01:51 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 23 Oct 2024 15:01:47 -0700 From: Daniel Machon Date: Thu, 24 Oct 2024 00:01:22 +0200 Subject: [PATCH net-next v2 03/15] net: sparx5: change frequency calculation for SDLB's Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com> References: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> In-Reply-To: <20241024-sparx5-lan969x-switch-driver-2-v2-0-a0b5fae88a0f@microchip.com> To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Lars Povlsen , Steen Hegelund , , , , , , Richard Cochran , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: , , , Steen Hegelund , X-Mailer: b4 0.14-dev X-Patchwork-Delegate: kuba@kernel.org In preparation for lan969x, rework the function that calculates the SDLB (Service Dual Leacky Bucket) clock. This is required, as the HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock from the core clock, using the sparx5_clk_period() function. The clock stays the same before and after this patch, only now, sparx5_sdlb_clk_hz_get() can be used for lan969x too. Reviewed-by: Steen Hegelund Signed-off-by: Daniel Machon --- drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 +- drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 10 +++------- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h index f117cf65cf8c..2a3b4e855590 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h @@ -552,7 +552,7 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx); int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, u64 rate); -int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); +u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c index df1d15600aad..98a3f44c569c 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c @@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx) return &sdlb_groups[idx]; } -int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) +u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) { - u32 clk_per_100ps; u64 clk_hz; - clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, - HSCH_SYS_CLK_PER)); - if (!clk_per_100ps) - clk_per_100ps = SPX5_CLK_PER_100PS_DEFAULT; + clk_hz = (10 * 1000 * 1000) / + (sparx5_clk_period(sparx5->coreclock) / 100); - clk_hz = (10 * 1000 * 1000) / clk_per_100ps; return clk_hz *= 1000; }