From patchwork Wed Oct 30 10:35:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?U2t5TGFrZSBIdWFuZyAo6buD5ZWf5r6kKQ==?= X-Patchwork-Id: 13856269 X-Patchwork-Delegate: kuba@kernel.org Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18A3D1E32D8; Wed, 30 Oct 2024 10:39:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730284775; cv=none; b=nzn1eGKN49B2/Ob0l/DsO9tmoAsD/BjbmFO2STZYi9aMIgaxHNvZFh2Wxf8Qh/RBJSssQWwKuseKlmJXXl5fdcFQVAu6qsnOyqG1uOB9QW6hfdJdqtLYg62mNXXt+8lzv2RFnF0/il5oxchhSm0ZaBQ321n5nCLk5e63i9oSurw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730284775; c=relaxed/simple; bh=upIrWDdL8pO6qm6ASOxxFGjG96LCi7LcA2BPi/+vQfQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XFiBOtE++xuziIAZ6rWvDOfp0MhKl4eCKv+YY22pX5SbFcSRM7CVOF/QDoZZHdm+FWKPUVEpBauD9z6bWSU4/k8zjoFxz2f3U6lpIMQyof8rB4vthHXCf7khIoINJ3yhsaOo8+wj8Xbo7t1pZF02ZPES6Ihwws+c3tCCUfbfQoI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=IWvqmxhQ; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="IWvqmxhQ" X-UUID: 3c7424ac96ab11efb88477ffae1fc7a5-20241030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=HJcJmoaUxY7nJ4Q2S1uk/s9xXqHeIao8IpYsxybz3hU=; b=IWvqmxhQzC+cPhkgxsXcY9IsN5vQynQr8jpxXjVMvuiVDDanIOh90HJGZv//bNcn6lU7P6Q6xDXGeyyX8S6vyM+JTg38tMDK8O01lL3H77cLJKGt1GhTw+IXaX4OWWWF05p0tiHcPpvlwAtqs9XaE962uq6n6y2qeppJ5IZsp+s=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.42,REQID:63ae9bca-a79b-42fe-a23f-2d00cb8087cc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:b0fcdc3,CLOUDID:e00e4807-7990-429c-b1a0-768435f03014,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: 3c7424ac96ab11efb88477ffae1fc7a5-20241030 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 156151274; Wed, 30 Oct 2024 18:39:26 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 30 Oct 2024 18:39:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 30 Oct 2024 18:39:25 +0800 From: Sky Huang To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Daniel Golle , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , , , , CC: Steven Liu , SkyLake.Huang Subject: [PATCH net-next 5/5] net: phy: mediatek: add MT7530 & MT7531's PHY ID macros Date: Wed, 30 Oct 2024 18:35:54 +0800 Message-ID: <20241030103554.29218-6-SkyLake.Huang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20241030103554.29218-1-SkyLake.Huang@mediatek.com> References: <20241030103554.29218-1-SkyLake.Huang@mediatek.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N X-Patchwork-Delegate: kuba@kernel.org From: "SkyLake.Huang" This patch adds MT7530 & MT7531's PHY ID macros in mtk-ge.c so that it follows the same rule of mtk-ge-soc.c. Signed-off-by: SkyLake.Huang --- No change since commit: https://lore.kernel.org/netdev/20241004102413.5838-8-SkyLake.Huang@mediatek.com/ Andrew Lunn has already reviewed this. --- drivers/net/phy/mediatek/mtk-ge.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/mediatek/mtk-ge.c b/drivers/net/phy/mediatek/mtk-ge.c index 9122899..ed2617b 100644 --- a/drivers/net/phy/mediatek/mtk-ge.c +++ b/drivers/net/phy/mediatek/mtk-ge.c @@ -5,6 +5,9 @@ #include "mtk.h" +#define MTK_GPHY_ID_MT7530 0x03a29412 +#define MTK_GPHY_ID_MT7531 0x03a29441 + #define MTK_EXT_PAGE_ACCESS 0x1f #define MTK_PHY_PAGE_STANDARD 0x0000 #define MTK_PHY_PAGE_EXTENDED 0x0001 @@ -59,7 +62,7 @@ static int mt7531_phy_config_init(struct phy_device *phydev) static struct phy_driver mtk_gephy_driver[] = { { - PHY_ID_MATCH_EXACT(0x03a29412), + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530), .name = "MediaTek MT7530 PHY", .config_init = mt7530_phy_config_init, /* Interrupts are handled by the switch, not the PHY @@ -73,7 +76,7 @@ static struct phy_driver mtk_gephy_driver[] = { .write_page = mtk_phy_write_page, }, { - PHY_ID_MATCH_EXACT(0x03a29441), + PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531), .name = "MediaTek MT7531 PHY", .config_init = mt7531_phy_config_init, /* Interrupts are handled by the switch, not the PHY @@ -91,8 +94,8 @@ static struct phy_driver mtk_gephy_driver[] = { module_phy_driver(mtk_gephy_driver); static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = { - { PHY_ID_MATCH_EXACT(0x03a29441) }, - { PHY_ID_MATCH_EXACT(0x03a29412) }, + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7530) }, + { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7531) }, { } };