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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Dragos Tatulea , Tariq Toukan Subject: [PATCH net-next 10/12] net/mlx5e: SHAMPO, Change frag page setup order during allocation Date: Thu, 7 Nov 2024 21:43:55 +0200 Message-ID: <20241107194357.683732-11-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241107194357.683732-1-tariqt@nvidia.com> References: <20241107194357.683732-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|PH7PR12MB5904:EE_ X-MS-Office365-Filtering-Correlation-Id: dde3378a-4f64-439c-669a-08dcff64cc72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: RFWaMje6ES5CssiRImALpFNBNRhGUT2/bXWmr9V8e437qb/SDIL4svvazpXnT9Kpm2N3nSRVWw8YkuC26V0fSd8IdSZydyI84KjWIYWJy+9R6SGnTiqYC9uO7OR5bSIIGubA/CsnHhcYVOUZ0g+QING76bi/jD2wwWNqozhpYWfh4YG7pU+/zFcdPqForRDcoF6q38Q5ZhhsbXv6bCIEta2NFSeD5ZEjVL9bHwMFGa+TEgLeNvPYWuIizu0UBmiFZLYj+O3AZCtgtl7rkrrvLvhxDEk1kMAnANUYcwd5hDzyFRM0bD0bI/9ZjqDUWOBKAShDMofji5KkB7dSh5zIQvtDPvENhXFWrI56t7QBlU0rE3+0AfznNlIgJcNw946ExwCrsfI6J1ADZYRSTO7mm+Hp6w9nmj6BZJfvU49syu1jppkcBeqE4uasaRjVDKSG9v5J7s/sqC93HAzUNK04Xg2kZvarp6/J1hfIEHVqgKDnLR787YyMCIB9xi0XlqIbgD7nkjN3hg786AIyZxdL6UwGz6XM0MMRszKJy5BTE0LyqJHVaI3UO4swsi/k/a74Nq/jdALA9UTm0BDpuokfBBwmtrbQf1DeOsRnMBytmJ5M1/x06aMfnbAv2chcjaDqxPo/i3V4O9lm85sCIx2Ie6cu3Odz325UTLeMejSdX1WdjHKWAHN8UuQ/d9CxNJUF5nLCQmQPDA0eVh2sWjZHzAahuKlzIobUeRC1k5WaWVBMYGGqNFCamf9SyUAF/Ar1mZgFWQDAtnQWBMijnx0HhvvfLNuxMjBpNYUySa+5vcBTM0h9joPo1QXsJaOUZ6m417l2gWWsUGZKM+aRR0+Kjpx3Q9iwU9yJ/Me1AiJYvi73QStEMgaYgMIYNzm2VzAHuDmGkq/2V9DWG4/PCcH0Uvhhi0Sr0J9JISRjhgA5QzMQlWtdNH9VmdFPsBcdh70xBt8UuvVP1ZFpEq0Z/5jb4PqQS8bjdvBvB6VX59QJuJFkMRmIbRCjf88kgxDPQ6FQbNRWkHHDpYZu8TfQ/eHIK+KvCP6YaCIJnK4JeVr4CgTyXj0JeGqR1+oOpILfPxrfeK9RLQgOvONklv4TgG3expbpbqjc1z5J3pxhXKXk0AVqqDvcrjZfTwHbXWZNI7irTJq1NH0RXG/y4WZvl1qID4E8Ajcq6SPd+cAvxFh1mkC8FwJhdOQhiGVb94iMX7e/kPyQMVnF92jgnL/vwNhx+e5IWtGVRQ+mOygJsIpbalRyO/wwUHh2mZOc4SWNEV8R6nAg6iNWxxotBUQrID5Iz+tzKccTn3S7YiWVrnN9WqGs9hN6/wA08npijSiDPEU0mfjoMHzgyynwm/h4zGJYr28jvgU1v0OCdPJG2vw1UyDy8TGafMnAiB/tEzNrSSm03Haf/ujjz+25s+pI/R6cRQ== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2024 19:45:57.0223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dde3378a-4f64-439c-669a-08dcff64cc72 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5904 X-Patchwork-Delegate: kuba@kernel.org From: Dragos Tatulea Now that the UMR allocation has been simplified, it is no longer possible to have a leftover page from a previous call to mlx5e_build_shampo_hd_umr(). This patch simplifies the code by switching the order of operations: first take the frag page and then increment the index. This is more straightforward and it also paves the way for dropping the info array. Signed-off-by: Dragos Tatulea Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/en_rx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c index 76a975667c77..637069c1b988 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c @@ -651,7 +651,7 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *rq, u16 pi, header_offset, err, wqe_bbs; u32 lkey = rq->mdev->mlx5e_res.hw_objs.mkey; u16 page_index = shampo->curr_page_index; - struct mlx5e_frag_page *frag_page; + struct mlx5e_frag_page *frag_page = NULL; struct mlx5e_dma_info *dma_info; struct mlx5e_umr_wqe *umr_wqe; int headroom, i; @@ -663,16 +663,14 @@ static int mlx5e_build_shampo_hd_umr(struct mlx5e_rq *rq, umr_wqe = mlx5_wq_cyc_get_wqe(&sq->wq, pi); build_ksm_umr(sq, umr_wqe, shampo->key, index, ksm_entries); - frag_page = &shampo->pages[page_index]; - WARN_ON_ONCE(ksm_entries & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)); for (i = 0; i < ksm_entries; i++, index++) { dma_info = &shampo->info[index]; header_offset = (index & (MLX5E_SHAMPO_WQ_HEADER_PER_PAGE - 1)) << MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE; if (!(header_offset & (PAGE_SIZE - 1))) { - page_index = (page_index + 1) & (shampo->pages_per_wq - 1); frag_page = &shampo->pages[page_index]; + page_index = (page_index + 1) & (shampo->pages_per_wq - 1); err = mlx5e_page_alloc_fragmented(rq, frag_page); if (unlikely(err))