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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jiri Pirko , Carolina Jubran , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 4/8] net/mlx5:Add no-op implementation for setting tc-bw on rate objects Date: Wed, 13 Nov 2024 20:00:29 +0200 Message-ID: <20241113180034.714102-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241113180034.714102-1-tariqt@nvidia.com> References: <20241113180034.714102-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA50:EE_|CY5PR12MB6371:EE_ X-MS-Office365-Filtering-Correlation-Id: 5518c6a7-410f-4d65-5b61-08dd040d41c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: AjpMZnC7uVYKxhGRYlJK/8WitGAARiLu4QDTvIng/WxP8VEyXfahhE0lXRqBM4I2fCXusajrWlcaKsggEqsG0Ie54dS/KQYQb8eRQ27jCoEPR1gFUSjZmRBHJBrsHGwAI+sXHJ+ZQkFin/tPAfYPkb7IIc1URS6Wtpa9ogTvetvxobIWN8SB5Ie54VVLd7AdnkPjq7lDaA7gb+T5CoqfD3v5TXvOBKfPlMzkrWKttymQrxxV17e4B1ps+IyomDsErtN2h2SJxXS6KZLopgCvFqBvt1vwKo9Bga2H1StERMlvCxD7eQ8kHFNkBCXcz3myjGfOXVSE+raxwI/j2RAWuImficLgkD7xhaGEt0WuP8e/q9Pq0MibgLkNePEZ9CgFqsUwlL5U++Z8nw+dUXXpRihUpa4CFTVEVH4E85+1UENEXmYh/rMtfNmfHHFMqmOMTrZSjPTUf/SmUqiHAfLtHaB2WmWhEOcg+2uYZDaQ0nHgBahXCw63ikNBt9EXS1Xo0fYhanqNDSARBq9MDUmv0BruVNoBZnmpaYCwOYf5czyTIpyfcv+rA0xXINELJEIqUlblEhJm7i75ZFj+QaizqWN1kht9aPr6Gh4kOCWXVbUx+8eUCw4FL8/Qw7HNwMSzqUXvvLJ9jK+S1yc3+mWJxtfA7kcBKfxZywde/qBgjBSxgjA3KyiObFfrAiVtVqIblm70CL1NBIGDhJr0425CDXWwODY+y7UMCq7F4gTbNmqdvPniKKU0Q7qJwGEDLjDnLFrMq711gFqO+FEDwFYcwYtHHw5ddhKO9PT09yAMT90AbVn/NKsfIbuExUrusEbtUlJAjJJuVWiC4Bl2H5nnTgfE1JJjUFV2U1jKksiRio2Q+fmQFRA0sQhfTAIDIIEMrpnvy+eBzLWZkv2KUomXI1YtcOdTbtZcLn5TNvSTj+R5RZv/O1Ps4/cqYKSIEZmbInpd91Cao04NLEHbQKUGhPFYeh4gDFTnWovunjDegq/xp1qSyCviiDiJ8F0svWRgP0engBfuGl7iyWfFLfmni+Gr4NolIDJXV4MXiJog8UCzAdPGuOYY56SMRz6klXtOqP2XXTZIv2SfIqcfII5sbe+16z5R5xDANKltsaSYzn1DBt9+mq/A2f+IOkJ9LMyN74tBcZF4oOiJDLUjuOmNedJtwK462a0FL3oQYemMyB1C1JWuSkLiQjFpiV2ILwZamQ3niySYx90IGn5Ql7zj5wGC24tLvBSV+q6FRxClqVMCXfaMrMsGM8hO9k9hbOSL/kzbymXkO3lQ20udIX+f4xzqkLIb3XSNCEWlojMpAHbXQR8ZvkURf6OEcU4LEXnPs7l88y8pUg2fDZGbTHJhzNvjpOl068xcdCKRCuEikhpELihBIO1XdPo+Em7vJknyNwseUbXXDvdR62WMVvGsww== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2024 18:01:53.9898 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5518c6a7-410f-4d65-5b61-08dd040d41c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA50.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6371 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce `mlx5_esw_devlink_rate_node_tc_bw_set()` and `mlx5_esw_devlink_rate_leaf_tc_bw_set` with no-op logic. Future patches will add support for setting traffic class bandwidth on rate objects. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 2 ++ drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c | 14 ++++++++++++++ drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h | 4 ++++ 3 files changed, 20 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c index 98d4306929f3..728d5c06d612 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -320,6 +320,8 @@ static const struct devlink_ops mlx5_devlink_ops = { .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get, .rate_leaf_tx_share_set = mlx5_esw_devlink_rate_leaf_tx_share_set, .rate_leaf_tx_max_set = mlx5_esw_devlink_rate_leaf_tx_max_set, + .rate_leaf_tc_bw_set = mlx5_esw_devlink_rate_leaf_tc_bw_set, + .rate_node_tc_bw_set = mlx5_esw_devlink_rate_node_tc_bw_set, .rate_node_tx_share_set = mlx5_esw_devlink_rate_node_tx_share_set, .rate_node_tx_max_set = mlx5_esw_devlink_rate_node_tx_max_set, .rate_node_new = mlx5_esw_devlink_rate_node_new, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 8b7c843446e1..db112a87b7ee 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -882,6 +882,20 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void * return err; } +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_leaf, void *priv, + u32 *tc_bw, struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, "TC bandwidth shares are not supported on leafs"); + return -EOPNOTSUPP; +} + +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, void *priv, + u32 *tc_bw, struct netlink_ext_ack *extack) +{ + NL_SET_ERR_MSG_MOD(extack, "TC bandwidth shares are not supported on nodes"); + return -EOPNOTSUPP; +} + int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, u64 tx_share, struct netlink_ext_ack *extack) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h index 6eb8f6a648c8..0239f10f95e7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.h @@ -21,6 +21,10 @@ int mlx5_esw_devlink_rate_leaf_tx_share_set(struct devlink_rate *rate_leaf, void u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_leaf_tx_max_set(struct devlink_rate *rate_leaf, void *priv, u64 tx_max, struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devlink_rate *rate_node, void *priv, + u32 *tc_bw, struct netlink_ext_ack *extack); +int mlx5_esw_devlink_rate_node_tc_bw_set(struct devlink_rate *rate_node, void *priv, + u32 *tc_bw, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_share_set(struct devlink_rate *rate_node, void *priv, u64 tx_share, struct netlink_ext_ack *extack); int mlx5_esw_devlink_rate_node_tx_max_set(struct devlink_rate *rate_node, void *priv,