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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jiri Pirko , Carolina Jubran , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next 5/8] net/mlx5: Add support for new scheduling elements Date: Wed, 13 Nov 2024 20:00:30 +0200 Message-ID: <20241113180034.714102-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241113180034.714102-1-tariqt@nvidia.com> References: <20241113180034.714102-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029928:EE_|DM4PR12MB7600:EE_ X-MS-Office365-Filtering-Correlation-Id: dd274793-69da-478e-3560-08dd040d3f80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: MOf47tO3p6sjE4uXHXaEfQ6RxZwjRKfvtWboAByNpJ8npCYo16W2VJ0c3e7cXJowO3ZmttRo+WfIFiVyck4AOkV2DsJN/bFnEgLC420nld+jffHpKl0KGsE+m5sflwWsw7Meu8k2Gn5e3cwsONXsa9HGHjDNWcF0cbNFWTnOLsrTVveCE5dhcoa1tnTsgza+dOLfi8HEDrhrMI+pSaWeN+YD3MwxWoLofQUCs7L5I5IdicnJr8GZIFXrGk0oI1QGIqSGWeYrYntc4atlCEfR+9Bu+S+9BMCqGBcVi/rtiYwYtKtWoF6qab2d6/EVYykCFT6Lxrau8P9+wJOOATA/NQEecou3mY4SCru4uFcmWRfV3IPpTSHef+NAM/7k//a8tmWrL9MENZJ1wy146BtIE92/YRaEII2CRAsXDE7mYC05tl2LDdTmVj5QRYwFPaeeO/NmbeUmDqQQJkTIEOVhGjiz+wNR76SswD8xPvO7zMuqLbgisaaFdQNDNPJxt8CKr64r1aF76ZPQJTlu/RvxUSw9Yyb2DRvrEUtCrk9fiEnfmrelVgS8CrKPAgP9hajBe34rrf74Y3Kmy41Dz6SyzHdvx+NpXJ+CxmQhleKuFkqchW/CPk/MJfIilErg4/AWNgMwTpN+ZASTDtrq50/+87bV5cdM6hSzapshBqpKgkxUorNNJaK/eSPalC5EBPQRdricgsBwWMxVgQT9y8PCqBMiNcuUNDvKw/EsguLjysQypiGzEIc1MIk27io709eq6dLRJviK2ckiJyyTV51rxDsAkkRU+hDp/yCCCsj8KK+QUwKYOBzCGYruLwObbrm+Tnt1fF3tTe41qyZPI6LWyZ9rzrbK4ncR1Wm0vOoDySdA4YqxOmbDozUWwNVzymuAdvUIXhO1XISfySQROTIdQPiwt0RyS69a/o4mFGJoX8OUAWPCRygs9UqiITIL6sFVF7Rswc7Zgec97TkKp9T3gusytNs5Pe4xAhubE22okV8XZZuJnK14Zr9e5k8vqc6kzppFhS41B/Tu1sIbzUIj7p5PTuI1hmc0Cyyh0eoEpEGBGiXAWgKGR/Gjqq+xxWq80UnLyuxw7EDv6syNcfH8wzG/Y7NbLcnvkCbjeHcp2HqPZY9XhAWNaPPqzLEp6gxr3GpOmJrwjQezmt4yqguNs70jr+tmdGPSTqoGgCsk5Ug61I4beN2e8dWnHUY4j08o175jyvV+b/cay8LbLmpYYhtUSiVAc4IsdFTtToBSQllA7q91GfjJUW9dukEnCzX6av/q9Gan4Hz0ahoJ36c5KLXGXPxBFecNNkJ9RY1SfxrvlDKC96jpdMAOCCwE7pWgWjQE74+zpRICJUKpYZ/o2982m+aQwisOU5ymNPi2Nf1BBQxaOJuUkEYhWMxtSj8iJaxQSh3Q9IZEW3skq3+VRA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Nov 2024 18:01:50.1056 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dd274793-69da-478e-3560-08dd040d3f80 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029928.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7600 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce new scheduling elements in the E-Switch QoS hierarchy to enhance traffic management capabilities. This patch adds support for: - Rate Limit scheduling elements: Enables bandwidth limitation across multiple nodes without a shared ancestor, providing a mechanism for more granular control of bandwidth allocation. - Traffic Class Transmit Scheduling Arbiter (TSAR): Introduces the infrastructure for creating Traffic Class TSARs, allowing hierarchical arbitration based on traffic classes. - Traffic Class Arbiter TSAR: Adds support for a TSAR capable of managing arbitration between multiple traffic classes, enabling improved bandwidth prioritization and traffic management. No functional changes are introduced in this patch. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/rl.c | 4 ++++ include/linux/mlx5/mlx5_ifc.h | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index e393391966e0..39a209b9b684 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c @@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN; case TSAR_ELEMENT_TSAR_TYPE_ETS: return cap & TSAR_TYPE_CAP_MASK_ETS; + case TSAR_ELEMENT_TSAR_TYPE_TC_ARB: + return cap & TSAR_TYPE_CAP_MASK_TC_ARB; } return false; @@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC; case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP: return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP; + case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT: + return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT; } return false; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index cf354d34b30a..87ec079ec83f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1103,7 +1103,8 @@ struct mlx5_ifc_qos_cap_bits { u8 packet_pacing_min_rate[0x20]; - u8 reserved_at_80[0x10]; + u8 reserved_at_80[0xb]; + u8 log_esw_max_rate_limit[0x5]; u8 packet_pacing_rate_table_size[0x10]; u8 esw_element_type[0x10]; @@ -4096,6 +4097,7 @@ enum { SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, + SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, }; enum { @@ -4104,22 +4106,26 @@ enum { ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, + ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, }; enum { TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, + TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, }; enum { TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, TSAR_TYPE_CAP_MASK_ETS = 1 << 2, + TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, }; struct mlx5_ifc_tsar_element_bits { - u8 reserved_at_0[0x8]; + u8 traffic_class[0x4]; + u8 reserved_at_4[0x4]; u8 tsar_type[0x8]; u8 reserved_at_10[0x10]; }; @@ -4156,7 +4162,9 @@ struct mlx5_ifc_scheduling_context_bits { u8 max_average_bw[0x20]; - u8 reserved_at_e0[0x120]; + u8 max_bw_obj_id[0x20]; + + u8 reserved_at_100[0x100]; }; struct mlx5_ifc_rqtc_bits {