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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jiri Pirko , Carolina Jubran , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next V2 5/8] net/mlx5: Add support for new scheduling elements Date: Fri, 15 Nov 2024 00:09:34 +0200 Message-ID: <20241114220937.719507-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241114220937.719507-1-tariqt@nvidia.com> References: <20241114220937.719507-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC0:EE_|SN7PR12MB7449:EE_ X-MS-Office365-Filtering-Correlation-Id: 1569a369-02af-4140-50b4-08dd04f93c05 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: 2mxpO8akVEwPIN0AMACKBZjd8Efrd4gs0I+7epf3y0tF728TZJnDc6+lRXBzs1uwfQErN48rEx78xFicZcekQ0Ey2DJeS4Ew46tuaquvJj3oR9d1vdGBnyXq8CO+ro/n0L1Knf05objSYQv8njFon9r2fI70osl3DlzYCgb5l1ZP8VNmCJUw8XcQGhOLRP1RfS215ste3YPfZVk99oWOmmemrdQwd2I59EOXsXJ0qwA6xiFCvpy3N7O56+37bsUevdCaDMoW9CUkgYpLWRvCporLQj+d+QaJ+IzLrycnjzX+6UeI+XOTDX2BaBct0zthips8ukasaDw2J/6oUYiHnvHo6vOqMduqMCFmxm6ypjjewtCqOtddGykTxsV1eBWsHH0OJBJshOYu9dSfDQSwkzreWpyGm5pF2p8BwyNMhoUhnMlmlcBUBBYiecW0MQujhtR7ihvrwn/PVSX0TUaYFGzvil9Eukiu45ixLDNLN7NFEWNpQjYrNyZnnKLHGG0B0UIAHylHLKFmmUv00Rfz3G2PWXwJH/6efWNdB8x5agwjhnz1UUhIbe70AfxqWSsUGJCbVqJ/xDY6Kb601fo6Q6AZNrg9TrINgCe8aiMqU1tUGncmxxYE8szkoEVVL+TwiGzXRNTfk67LVnfxb/jADM0cJ5fXzpdCPdDs3XVH7ZlI91+oYP8qVJeDTmm177rlFckGJ+bFkd7SYfs6oGx0+yiLfQQvj9V89M3Q5ZUwWVPDTYVAyU1E+102i145su/mZypkBumjGtxBfxCSj6fJ1v5YNy14W9T5e9dmib+DgEunSkipvw6QbZby7NKgev7N2bm0ufxI5+r0tkNWNdRB08QuE8Mp0P2SfVLz8xY/2kMJFvrHmERfcBNWmEgiXXQAiuuogM3JJzFenpqilxJMydBmncun9j48bZpbUVuc03K6botRsr8gyVwDsuRQBm4KgCW/APuoJQwMJD5GNiupjNz+mOmsEypVUbQspVi/COlzftQIOn1auV2XTvg9X1jYaqyMOBZxGKN6SvO9RuGBHrCzQ8N2x2MzoXKK0nag6kUmADgaooRx4UxeXqsUJlJysC0nyvZZQK49q2tvBvmIHoQ/RmFhI5Qw0rQfHuwqQf06yznW8wZzmDz2XwQilAXerq/pEBNiIRDC6cCS5CgmntyTwq3CUvq6z8RiZ1YNiZnheQcomVNxZ0aOiD4S+x5hCiKoy0q7a7sks8TOe2QypKTjsJfbREo82GWIAD1BDC4m4Vph2kwugh7OGaJM/gPJ0hFzfcC/5kfDGBIzn72mKb0mDVAeSWrCsaKmpek52tcANSuoT6tmSzTqCnOS37Zra0R1h9skqPQRC26LSFOvAINPDEJZiguNZaOE0pToJCYWuMfhSAawxkw3cvVPOxBUcSq8UNk8L1SX8LHahu77mw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Nov 2024 22:11:05.5733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1569a369-02af-4140-50b4-08dd04f93c05 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7449 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce new scheduling elements in the E-Switch QoS hierarchy to enhance traffic management capabilities. This patch adds support for: - Rate Limit scheduling elements: Enables bandwidth limitation across multiple nodes without a shared ancestor, providing a mechanism for more granular control of bandwidth allocation. - Traffic Class Transmit Scheduling Arbiter (TSAR): Introduces the infrastructure for creating Traffic Class TSARs, allowing hierarchical arbitration based on traffic classes. - Traffic Class Arbiter TSAR: Adds support for a TSAR capable of managing arbitration between multiple traffic classes, enabling improved bandwidth prioritization and traffic management. No functional changes are introduced in this patch. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/rl.c | 4 ++++ include/linux/mlx5/mlx5_ifc.h | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index e393391966e0..39a209b9b684 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c @@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN; case TSAR_ELEMENT_TSAR_TYPE_ETS: return cap & TSAR_TYPE_CAP_MASK_ETS; + case TSAR_ELEMENT_TSAR_TYPE_TC_ARB: + return cap & TSAR_TYPE_CAP_MASK_TC_ARB; } return false; @@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC; case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP: return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP; + case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT: + return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT; } return false; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index cf354d34b30a..87ec079ec83f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1103,7 +1103,8 @@ struct mlx5_ifc_qos_cap_bits { u8 packet_pacing_min_rate[0x20]; - u8 reserved_at_80[0x10]; + u8 reserved_at_80[0xb]; + u8 log_esw_max_rate_limit[0x5]; u8 packet_pacing_rate_table_size[0x10]; u8 esw_element_type[0x10]; @@ -4096,6 +4097,7 @@ enum { SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, + SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, }; enum { @@ -4104,22 +4106,26 @@ enum { ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, + ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, }; enum { TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, + TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, }; enum { TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, TSAR_TYPE_CAP_MASK_ETS = 1 << 2, + TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, }; struct mlx5_ifc_tsar_element_bits { - u8 reserved_at_0[0x8]; + u8 traffic_class[0x4]; + u8 reserved_at_4[0x4]; u8 tsar_type[0x8]; u8 reserved_at_10[0x10]; }; @@ -4156,7 +4162,9 @@ struct mlx5_ifc_scheduling_context_bits { u8 max_average_bw[0x20]; - u8 reserved_at_e0[0x120]; + u8 max_bw_obj_id[0x20]; + + u8 reserved_at_100[0x100]; }; struct mlx5_ifc_rqtc_bits {