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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , Jiri Pirko , Carolina Jubran , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next V3 5/8] net/mlx5: Add support for new scheduling elements Date: Sun, 17 Nov 2024 22:50:42 +0200 Message-ID: <20241117205046.736499-6-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241117205046.736499-1-tariqt@nvidia.com> References: <20241117205046.736499-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|DM4PR12MB5841:EE_ X-MS-Office365-Filtering-Correlation-Id: eab02155-f510-4a3a-6b65-08dd0749b16d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: Za0amxjyc4GXNpe8t9mRykVagV1Ezt+XKbBjgfwrAPlsu1ozfTpjFaqoFUoEKTp9d4H0aUpfTzDtOQqVFqOCaXFyxZZRhpfSQmetsDw18l0kO8mVGbBzTub+y7z4gZpBJRF278Co/jLVCNwRtlKOmRx+nANVhnv735WmJUoF9mKPkzPjbKwVjSlQ0XLKS6rgGm3gBNFwW4TA+Dt2nWUjqi2Y921ao4h+GhwDJyH82MC5KPYDZ2chT1uMreWRYsGcRcQ51TGAVMVrEkZrAXJ+QRXoFNANuhIE1L3GJQbperAJHFdpxLJxBEI5du1tJwU3o/tH8MtJeoHcuZiWd5J54WHnH+Tz5VXIft2xSz6GCjsVIepdHAc2tppPcChseowx+uYdQ4B7Fiz8vngP66Wziy76IeHDZuVeCdk3Mm8KKyHDyW1HaypyIcMZ/YkX2+y/jWEqqiKFQPYYqP9jmkQHRh6+0qU8HKxi46tlYNLQ/sqh+VjWzV0D4LSGFkq7iaR9DAl1xikCfATWbY7EUSRzG0pcFTN8AA13zDyvU+c0mpZ67emkUZUwXN1nhl7v7Ndo3IiI5ITsTS52xrRIPu8p7/fhlxbPDPuNZZvRhd8Af/9W/1iOHmPg2ff9mD6/vad3EhyHeBygwtslx7KSJbhzACcO09no/wEhDZopP385IOKvVpS/wQ+4mazb2Kq+UHGyL3KFEhPPhwECKbXd10kwtrOPz9i0MUh8VF+P9j/gpp7YJV1EEbiD7+qUmRSsuXWVkygIKJeQvuMdVrXWprE7ZvvHFMYbjAkdDz/+7TBFUxk4IQkVzGesHSnP0UE1U8QYK8eoSW3pydk7CV9IRE2OGh0ELVys4JVzocgMY9da/K87ilqarXZWQi2Un8+acsfKSxlEdbR/XOzLAAQkxlHhTiBtsDhIVeFB+uuHO5jb8ae9ip7mdigiuHm4xdUn+G0lEbPWvOm9lWOZeMeX1gJdjCPffxe6If2QXdY6Z8FZCOZYI8xkVfj8GYDtguW67LuLOuDJ1ZZIP6QVKaSIBjBYG5dP7JYmJxejBvA0aL05Idv61ZuEHMW9V87NxTAQwFe8REN1rNtkqzypo6OlnGlV0BO6RT5W9FioPft0RDAvQ4timy9eMR86GXA7Un6bxWDyauoofhNFK7n+xiH97ujmGt0H7hrHnL6Rx6AuGEiFoAmc2rp3lTkpaZP/a9S6uvwtCjtzPwJKydzg0VQDM9yvmAeCZPzh/T31UljRfnrI1dj3H9dIkJnaBfwKMOrsEt9GkHRgTyKvILmxmOhTQRnuXdAe+cr7rrfhlrS7qkba8Eukrv9FKe6xocO5c65sXu87RpJTb7yLzq7kRDou2r4j/Tt0DG27vvp1ODGXPtPzEx6fX/7Wz5XBxkj3G+88PnteYDikHCHgHS+2gQdd7DSFqA== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2024 20:52:04.5661 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eab02155-f510-4a3a-6b65-08dd0749b16d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5841 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce new scheduling elements in the E-Switch QoS hierarchy to enhance traffic management capabilities. This patch adds support for: - Rate Limit scheduling elements: Enables bandwidth limitation across multiple nodes without a shared ancestor, providing a mechanism for more granular control of bandwidth allocation. - Traffic Class Transmit Scheduling Arbiter (TSAR): Introduces the infrastructure for creating Traffic Class TSARs, allowing hierarchical arbitration based on traffic classes. - Traffic Class Arbiter TSAR: Adds support for a TSAR capable of managing arbitration between multiple traffic classes, enabling improved bandwidth prioritization and traffic management. No functional changes are introduced in this patch. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/rl.c | 4 ++++ include/linux/mlx5/mlx5_ifc.h | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index e393391966e0..39a209b9b684 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c @@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN; case TSAR_ELEMENT_TSAR_TYPE_ETS: return cap & TSAR_TYPE_CAP_MASK_ETS; + case TSAR_ELEMENT_TSAR_TYPE_TC_ARB: + return cap & TSAR_TYPE_CAP_MASK_TC_ARB; } return false; @@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC; case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP: return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP; + case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT: + return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT; } return false; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index cf354d34b30a..87ec079ec83f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1103,7 +1103,8 @@ struct mlx5_ifc_qos_cap_bits { u8 packet_pacing_min_rate[0x20]; - u8 reserved_at_80[0x10]; + u8 reserved_at_80[0xb]; + u8 log_esw_max_rate_limit[0x5]; u8 packet_pacing_rate_table_size[0x10]; u8 esw_element_type[0x10]; @@ -4096,6 +4097,7 @@ enum { SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, + SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, }; enum { @@ -4104,22 +4106,26 @@ enum { ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, + ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, }; enum { TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, + TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, }; enum { TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, TSAR_TYPE_CAP_MASK_ETS = 1 << 2, + TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, }; struct mlx5_ifc_tsar_element_bits { - u8 reserved_at_0[0x8]; + u8 traffic_class[0x4]; + u8 reserved_at_4[0x4]; u8 tsar_type[0x8]; u8 reserved_at_10[0x10]; }; @@ -4156,7 +4162,9 @@ struct mlx5_ifc_scheduling_context_bits { u8 max_average_bw[0x20]; - u8 reserved_at_e0[0x120]; + u8 max_bw_obj_id[0x20]; + + u8 reserved_at_100[0x100]; }; struct mlx5_ifc_rqtc_bits {