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Mon, 18 Nov 2024 06:45:46 GMT Received: from yijiyang-gv.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 17 Nov 2024 22:45:42 -0800 From: Yijie Yang Date: Mon, 18 Nov 2024 14:44:01 +0800 Subject: [PATCH v2 1/2] arm64: dts: qcom: qcs615: add ethernet node Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20241118-dts_qcs615-v2-1-e62b924a3cbd@quicinc.com> References: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> In-Reply-To: <20241118-dts_qcs615-v2-0-e62b924a3cbd@quicinc.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran CC: , , , , Yijie Yang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1731912338; l=1557; i=quic_yijiyang@quicinc.com; s=20240408; h=from:subject:message-id; bh=0qZUPdGJk7bBM+UxhZdM6wcIbpEizh3WpNn2B2lAzws=; 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Signed-off-by: Yijie Yang --- arch/arm64/boot/dts/qcom/qcs615.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi index 868808918fd2cdf3f23fcb43ead61b2abfc776f7..e429a012428701b1240556c919c630382b3ee8ce 100644 --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi @@ -375,6 +375,38 @@ soc: soc@0 { #address-cells = <2>; #size-cells = <2>; + ethernet: ethernet@20000 { + compatible = "qcom,qcs615-ethqos"; + reg = <0x0 0x00020000 0x0 0x00010000>, + <0x0 0x00036000 0x0 0x00000100>; + reg-names = "stmmaceth", "rgmii"; + + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "rgmii"; + + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x1c0 0x0>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <20480>; + + status = "disabled"; + }; + gcc: clock-controller@100000 { compatible = "qcom,qcs615-gcc"; reg = <0 0x00100000 0 0x1f0000>;