From patchwork Mon Nov 18 20:24:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13879024 Received: from DB3PR0202CU003.outbound.protection.outlook.com (mail-northeuropeazon11011007.outbound.protection.outlook.com [52.101.65.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73FDF1E7C16; Mon, 18 Nov 2024 20:25:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.65.7 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731961505; cv=fail; b=o8scxO2SjX366mBfQDJKQ6eR3fwEV91jlUCBJtGJEOn4P5k7fYFosmRguIK7HZmLzAYgKLHte3gEDKKIBO62zY1O7ktUL29/WRj13y5azWiREzrYp1Wr8Qn4Q7Ndwn/0zyY80T7P+uFaMtt3PuDGHe5Y3SZ1Z5SLW7IZyjYb/IY= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731961505; c=relaxed/simple; bh=4ra43ajdZ13zOevxF3sZOj0QfYfjuGfS9I8FxESNjmg=; h=From:Date:Subject:Content-Type:Message-Id:References:In-Reply-To: To:Cc:MIME-Version; b=qj74d81HWDgxhirG87F2Mns5Xf+Vb+NosNULI72YWgfsAXolsIzS6FMliXcQsv1J3AJZBDL61F8sGeYPo6y1XmWFc9LPwt0YEZIGvLstSkETHIQoeFtoaJY0bgxnr22D3v86shZnqajxZcRMutll+IgoLf5tqJFOa5pFz+HLTJY= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com; spf=pass smtp.mailfrom=nxp.com; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b=CP1M+vqR; arc=fail smtp.client-ip=52.101.65.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nxp.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=nxp.com header.i=@nxp.com header.b="CP1M+vqR" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=DbunO8LocqFkqUQkgDbcq8s7ZCY+6EoOiwjshZ1QvU1JF7JwL2HinUsYFBHpV6V8hWlO1V4YNjPznoUmnaX2q6PHUNkr+xpxIIzpzntpxVkxRWP1S3gwUHa6/1m5tjSHF7E6VXu2X9ZEo1g+OrmsM1Z7a+ImJIVPsiqcxFY4ZZ/9Df8mTIoAnZqXc+FA3BXOq4n+f4E17rdDJKqi6OQEWn62Zd+s/z/yWutqM2oMLeKN28S0BPzITBqufEtMIbnaOfATtwzLH/OJcXToxpWGCkm1t/4aByNSDn8ncH7N8dNBtzEE0yKwvZwC9JZq+SFi27WK+SR/ZrfuIsDp0OvBKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=AWivA6yo1jfUnlS+ZnSNsZ+1Zbs/HQey6rwr9gVfS+w=; b=wCM4T7hbgrtKC1TZPDUntMtISzf9LFRKDvKB9GDDVeVuXj87QZ54TQR2BnxRJ+AcdpK0tikQKnVz0kr08zBd2AggYFiIiRFPaSwx8TgQ2LHSjM3t8Yorrt4HSYQs4xvuVbyvnJegDU+nsjwqMxLjZzxy31P84RSTnGtuKuHIDAju71n0v42uzh7C0am43kSXhNgRoA+GymVeKRyBhz0QUVp9sZb9lwOPaU1Z8xuCDkYJRdp7M7Ck2B7jiUgMhrrsucEi/qab6hUvlUDtbaxFyqkJC2vYrcrUMvk6jVZsH3K9jvJuIJgrH0NDb0XfmTL00GGCfuF5WYriKxo+xy3pBA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=AWivA6yo1jfUnlS+ZnSNsZ+1Zbs/HQey6rwr9gVfS+w=; b=CP1M+vqRZBlKfyZCAn7zIPJinc4OY9zlrxresq8j075su2pjIa3Hc7ZWGjzn/YX4oNaZxUPp8X5hVurAuk5SIBy9dnyXTVvIEciT1zS2vER6oQeUxZgHs3EzE2MaOd2iA/+pS0BoYtVnh91YkgOF+vrDOH4Qk37QSRXpyeK9PjmejO5R88ZSD/ukWK1BxSyM3sXLrUcdC7oaEyqqR3doURiogSH2YTVoIlvJCYgf9r2BDnlD9qOGjUq742UyYo6A1O+vBhc2BtqdPlqqvGujSiJVslZ1nPNcImd6Ve16rLVp4d3IIMWHh5Zy27SzGWX1MVveJjaPHbmYLpInc9CneQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; Received: from PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) by DB8PR04MB6858.eurprd04.prod.outlook.com (2603:10a6:10:113::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8158.21; Mon, 18 Nov 2024 20:25:00 +0000 Received: from PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06]) by PAXPR04MB9642.eurprd04.prod.outlook.com ([fe80::9126:a61e:341d:4b06%4]) with mapi id 15.20.8158.021; Mon, 18 Nov 2024 20:25:00 +0000 From: Frank Li Date: Mon, 18 Nov 2024 15:24:28 -0500 Subject: [PATCH v6 2/2] PCI: imx6: Add IOMMU and ITS MSI support for i.MX95 Message-Id: <20241118-imx95_lut-v6-2-a2951ba13347@nxp.com> References: <20241118-imx95_lut-v6-0-a2951ba13347@nxp.com> In-Reply-To: <20241118-imx95_lut-v6-0-a2951ba13347@nxp.com> To: Bjorn Helgaas , Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, Frank.li@nxp.com, alyssa@rosenzweig.io, bpf@vger.kernel.org, broonie@kernel.org, jgg@ziepe.ca, joro@8bytes.org, l.stach@pengutronix.de, lgirdwood@gmail.com, maz@kernel.org, p.zabel@pengutronix.de, robin.murphy@arm.com, will@kernel.org, Robin Murphy , Marc Zyngier , Frank Li X-Mailer: b4 0.13-dev-e586c X-Developer-Signature: v=1; a=ed25519-sha256; t=1731961482; l=8650; i=Frank.Li@nxp.com; s=20240130; h=from:subject:message-id; bh=4ra43ajdZ13zOevxF3sZOj0QfYfjuGfS9I8FxESNjmg=; b=kVJL+NAbutqgxd1uX5vfeVGPOWjJzFuZ3kDhota2Ss/v1k67g0PhGlGVplho1Uj/IPAHMIK4D GOWqHTe/+bPAIdIrP9YpvST9YOZYtAGl2SPErx37UReKK/oiXNHQzup X-Developer-Key: i=Frank.Li@nxp.com; a=ed25519; pk=I0L1sDUfPxpAkRvPKy7MdauTuSENRq+DnA+G4qcS94Q= X-ClientProxiedBy: BYAPR02CA0048.namprd02.prod.outlook.com (2603:10b6:a03:54::25) To PAXPR04MB9642.eurprd04.prod.outlook.com (2603:10a6:102:240::14) Precedence: bulk X-Mailing-List: bpf@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PAXPR04MB9642:EE_|DB8PR04MB6858:EE_ X-MS-Office365-Filtering-Correlation-Id: 167198d5-c537-4224-bdec-08dd080f139c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|52116014|376014|921020|38350700014; X-Microsoft-Antispam-Message-Info: =?utf-8?q?aqwQoYnyjTvJVqpcnD92Y5mr2U2fL7p?= =?utf-8?q?NemmFj63NZuDt2icNKS37dpD5n0kM+MBGRoLir9ozU58JSFpFpbTznsgRC2IXJxZ7?= =?utf-8?q?eoWgFkFMEPBiCWX95HvXBqXqYQnIEmUzqjlQuSNKlrEG1IcmDcqpzcIc1578/SY1t?= =?utf-8?q?8kpZtU5TrarX3nYbX6ncu6DpJR5cKLrPmGZecwB8UJyznoN2AVX7FhHC8ZrxGbfNh?= =?utf-8?q?grVkAu+c2xTS1j2I3wE2qRC+0piZzOX+FDNhXTpyBK59zTAy6zzA7rU5WZAqFkB6D?= =?utf-8?q?phmGhMcoFVnRaugV4/DZBbX/MpHUjB93w0TY3N4HVo1EmCyFyrodVKCpH7dzNzkE3?= =?utf-8?q?T4YFvIeLJ2Rezs0guZ2KBJpnVfiJIzf6p8/7ScjhuU6D7VeWr09Ui/P1icEhMznIr?= =?utf-8?q?2qRDcFz5st3Ic/lpPLDxTLgCz7z5WRQfUNN0FtOE9ypfdr88OR/Kxv9H8Jl9hGsMy?= =?utf-8?q?pNSSqToKrn0tbhhlo+JCwxu1aMI1xHKGkGo0RGNAuvUnLQdZ/gj13yz8kuJxUyNoX?= =?utf-8?q?VaTnzoGVIljT73b5H5rcfkUqUrqagCcFrZpRtkd2kMuVR1eypUQNtN67pwFuqCwaR?= =?utf-8?q?Rs+RUJGFapWiem24j0+hrkM+FXfFOw4G+E8GVx9K8dGbYkb/QSNE01oeVEw+TEze/?= =?utf-8?q?YG4jF3wEO4DB/a7Kou0+/gXtsDtYl3ReWu3POgSmnJb+cQ5vy75qKJSUEiSRRUBUp?= =?utf-8?q?BXSj8+j1W8GxQBFs6eSvozzlcNjJq5r56u2v64t50/7CGS9kFwZekQBnya57Q51j6?= =?utf-8?q?Zp1bF198eLeKCB6gCHfoJVxzKaLkXprMfITjWslai8G0GjRLi9Shz005hJS/BJXLC?= =?utf-8?q?xPuwgJQeFsKe4UMKUADBW2NJNhgMJcCKQIZry7BZ7MFhDf9w9GyA7fjgo4LqHQ/1Y?= =?utf-8?q?ih+6nM9cuNOnqiuoEx5dydf7+hILtOF6CNlMzfiwmgCCUZA79fIXp688UVY2GLLYo?= =?utf-8?q?YgAnurc3mAp482RMAobF8ok9ovhQ8oDnErhwhAEAtfJP+Ut94P8bC+KfK/zuqe+xo?= =?utf-8?q?/BRqiYC3+D9JkCULgK9elcr9W6Mv21BF4H0keMoKqFxEjjIWnvhZ3vGj1F1KxD2+T?= =?utf-8?q?eDaQOdMAPDg8JNzF279KD9d9jO+4pd0vuhfOPQ/bPQRkJkfOtVDKF/2u9lvswyPZq?= =?utf-8?q?aCFna/GhYaAjKAdfCGF2LlAevCrlRBCbaL+TKjTSsO8zTrICXmrzrrZz7FpYYJSu6?= =?utf-8?q?AZAAJd6APLkBymQ++a4NeZHFpbxO2ndoEYwbVLCc0pcCalpKO+f3EwO+rCKuJpaxs?= =?utf-8?q?VJuNUeKIcdKGfYavad+VnG9woUYACtmj16wflDw16fFZaJFum9U2gtbxXpJXRlQZz?= =?utf-8?q?bvWIGj/hkvBR?= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:PAXPR04MB9642.eurprd04.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(366016)(7416014)(52116014)(376014)(921020)(38350700014);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?fuiEJ3wV6Hnihmr6Bs5Zko079+hS?= =?utf-8?q?k4NeSY+8Jk8aPD1F85Rmx5u1gY5R3m4gAYd2WqGIiOtrZO3sXhs5LKW5X6w23wHBb?= =?utf-8?q?kxolMb4OiLLpKmUhdEu7wWK8QN1P68BEwegZuDMMAminOvgw/qnQVD9Qa2upAWL4Z?= =?utf-8?q?qwGPyZ0xF94KuyoCC2Pj8nbHiV8ABYp0tdtHnN6NW6jzKZSEIXifmrN/glHr5xImF?= =?utf-8?q?HccH5ksKEKSgRDgUU67WZt2R/VBRUIOA3wlzX9bJR4xIucP/zu9asUT9fLBs4YCSJ?= =?utf-8?q?EG4doLP4I6CpczpphppS2WcfnERYocFu0ofon1ltwey6ZyOEvYiKczZuaykLJiVb5?= =?utf-8?q?PV7WjauUZ2P9A5XaL5/NdIjPjYk/IQmNVwotfulX+8Ko+MOO1z27F44Mnjxc0p+4/?= =?utf-8?q?T8KW2WLDrkta1LB/bWEwlKQzr+F2OzvV5ZwBMJmmGnndVv8OWCxc4H5hfE4+pMKFf?= =?utf-8?q?517VAHRW2iUPtIfj8CAAJp0AkOPRXnrMjPOSvz72rxlisWqyHxWnoj4Loq3/cG2Rv?= =?utf-8?q?w5snxmZc5FRkYd3dUiS2p2DYumQy0h0uS+lJ/duG/tJDy9ttRdZydwSohonmmniuD?= =?utf-8?q?+S4kRUfyN6kz0jIQd6H8E1TkKVQ2ZOFSNKDSyeOKvggdNd1PrRKkyMuEhbPXNFdTy?= =?utf-8?q?JyMLpRg3+vwOGBZRCoZSoUEkVdHmXJtA7mhEdoVw0rVfxPUwujvTa8X+yM7MSGYAE?= =?utf-8?q?mMB3pRkb6u7xssUr+Xtoc6eVe5SkgrWVeoGbXSjVyDz5kdNvYnXCuqufAouqgSwmp?= =?utf-8?q?g4hqUoYijA5oqTWAAB0aX8tKFENsx8iqK+ASOxqD31xA3ZHuqpBN9nR+DgpmM+eXf?= =?utf-8?q?s2DkkPn6BGLtKOW0rJ6K+B3vBPjdZkqlI7Ar+N4Qv78OfwkqAwdzG1j79gMR8j1ZU?= =?utf-8?q?qk0Kxgk+qPtDzizNh5Ip9yD9kFbiXuzDOfEwXFw07c5OBNiZRpCjlO3MVXehAAj2N?= =?utf-8?q?MnkS4Jrkdh3GOuDp3w9/LOczKryJl1G8BGtc/QeAqarGVsJGA/bdOogfrZjg1J0Y/?= =?utf-8?q?P9OtikbyCq+qddglGBqr8qWd1AiP09PaFtjMxmTCTgh7gdoe9H8ZPXRbX0pwzjgIs?= =?utf-8?q?lHBJCLMjefThPCJiMug9/QVJY8c1UbBO/hMK4hmlgGLXRc73xeoTKvO+T2lntpTlc?= =?utf-8?q?GGZ8qfaOgHkgCcwJQkwpVNQQxLCLFy0FjFfUCyT4pQqqFjjkhOC4EB20AEpvLj/LY?= =?utf-8?q?dAm/yvBiaIBVz0EE2ARWIpUE4h69wNdL14WkdxV9TRKN3nRYQu4tELSCVc0iUS2XW?= =?utf-8?q?ZGfr8qugQrFni9o1cvZrTJWorHGY32UPZ86tXxzNVjBknTIE4Exz1ajrO3BEoUn0o?= =?utf-8?q?p3zrvUXnnD+UnQnmhj8JO+UjU0zu22wEC4rN1cyb+gXaeYj075zFl2MCBRjGWnZOy?= =?utf-8?q?ZIzUQgZY9Xjt6rsIvpd1ttbAwkRwn8NUYocRREZ3Zh5EODP3nmg6hnMQQo+OH3uOC?= =?utf-8?q?5ppnC9z0euPqcOUZC6bJIAU0MUrc8ICkLxWMxhYwvW33MHcibfhBDpDY=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 167198d5-c537-4224-bdec-08dd080f139c X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 20:25:00.4414 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ek6AZExrO8kGF6/GxsARCjlhq/3+Mc1eOrniEAxQzjnqiB38KcopwSb/F8I9QFeiqqwcAWWg+2nUFqJq+sLaAw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB6858 For the i.MX95, configuration of a LUT is necessary to convert Bus Device Function (BDF) to stream IDs, which are utilized by both IOMMU and ITS. This involves examining the msi-map and smmu-map to ensure consistent mapping of PCI BDF to the same stream IDs. Subsequently, LUT-related registers are configured. In the absence of an msi-map, the built-in MSI controller is utilized as a fallback. Register a PCI bus callback function to handle enable_device() and disable_device() operations, setting up the LUT whenever a new PCI device is enabled. Acked-by: Richard Zhu Signed-off-by: Frank Li --- Change from v5 to v6 - change comment rid to RID - some mini change according to mani's feedback Change from v4 to v5 - rework commt message - add comment for mutex - s/reqid/rid/ - keep only one loop when enable lut - add warning when try to add duplicate rid - Replace hardcode 0xffff with IMX95_PE0_LUT_MASK - Fix some error message Change from v3 to v4 - Check target value at of_map_id(). - of_node_put() for target. - add case for msi-map exist, but rid entry is not exist. Change from v2 to v3 - Use the "target" argument of of_map_id() - Check if rid already in lut table when enable device change from v1 to v2 - set callback to pci_host_bridge instead pci->ops. --- drivers/pci/controller/dwc/pci-imx6.c | 178 +++++++++++++++++++++++++++++++++- 1 file changed, 177 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 94f3411352bf0..725db9987fba8 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -55,6 +55,22 @@ #define IMX95_PE0_GEN_CTRL_3 0x1058 #define IMX95_PCIE_LTSSM_EN BIT(0) +#define IMX95_PE0_LUT_ACSCTRL 0x1008 +#define IMX95_PEO_LUT_RWA BIT(16) +#define IMX95_PE0_LUT_ENLOC GENMASK(4, 0) + +#define IMX95_PE0_LUT_DATA1 0x100c +#define IMX95_PE0_LUT_VLD BIT(31) +#define IMX95_PE0_LUT_DAC_ID GENMASK(10, 8) +#define IMX95_PE0_LUT_STREAM_ID GENMASK(5, 0) + +#define IMX95_PE0_LUT_DATA2 0x1010 +#define IMX95_PE0_LUT_REQID GENMASK(31, 16) +#define IMX95_PE0_LUT_MASK GENMASK(15, 0) + +#define IMX95_SID_MASK GENMASK(5, 0) +#define IMX95_MAX_LUT 32 + #define to_imx_pcie(x) dev_get_drvdata((x)->dev) enum imx_pcie_variants { @@ -82,6 +98,7 @@ enum imx_pcie_variants { #define IMX_PCIE_FLAG_HAS_PHY_RESET BIT(5) #define IMX_PCIE_FLAG_HAS_SERDES BIT(6) #define IMX_PCIE_FLAG_SUPPORT_64BIT BIT(7) +#define IMX_PCIE_FLAG_HAS_LUT BIT(8) #define imx_check_flag(pci, val) (pci->drvdata->flags & val) @@ -134,6 +151,9 @@ struct imx_pcie { struct device *pd_pcie_phy; struct phy *phy; const struct imx_pcie_drvdata *drvdata; + + /* Ensure that only one device's LUT is configured at any given time */ + struct mutex lock; }; /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */ @@ -925,6 +945,154 @@ static void imx_pcie_stop_link(struct dw_pcie *pci) imx_pcie_ltssm_disable(dev); } +static int imx_pcie_add_lut(struct imx_pcie *imx_pcie, u16 rid, u8 sid) +{ + struct dw_pcie *pci = imx_pcie->pci; + struct device *dev = pci->dev; + u32 data1, data2; + int free = -1; + int i; + + if (sid >= 64) { + dev_err(dev, "Invalid SID for index %d\n", sid); + return -EINVAL; + } + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); + + if (!(data1 & IMX95_PE0_LUT_VLD)) { + if (free < 0) + free = i; + continue; + } + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + + /* Do not add duplicate RID */ + if (rid == FIELD_GET(IMX95_PE0_LUT_REQID, data2)) { + dev_warn(dev, "Existing LUT entry available for RID (%d)", rid); + return 0; + } + } + + if (free < 0) { + dev_err(dev, "LUT entry is not available\n"); + return -ENOSPC; + } + + data1 = FIELD_PREP(IMX95_PE0_LUT_DAC_ID, 0); + data1 |= FIELD_PREP(IMX95_PE0_LUT_STREAM_ID, sid); + data1 |= IMX95_PE0_LUT_VLD; + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); + + data2 = IMX95_PE0_LUT_MASK; /* Match all bits of RID */ + data2 |= FIELD_PREP(IMX95_PE0_LUT_REQID, rid); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); + + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); + + return 0; +} + +static void imx_pcie_remove_lut(struct imx_pcie *imx_pcie, u16 rid) +{ + u32 data2; + int i; + + guard(mutex)(&imx_pcie->lock); + + for (i = 0; i < IMX95_MAX_LUT; i++) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, IMX95_PEO_LUT_RWA | i); + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); + if (FIELD_GET(IMX95_PE0_LUT_REQID, data2) == rid) { + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, 0); + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, i); + + break; + } + } +} + +static int imx_pcie_enable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + u32 sid_i, sid_m, rid = pci_dev_id(pdev); + struct device_node *target; + struct device *dev; + int err_i, err_m; + + dev = imx_pcie->pci->dev; + + target = NULL; + err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", &target, &sid_i); + if (target) + of_node_put(target); + else + err_i = -EINVAL; + + target = NULL; + err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", &target, &sid_m); + + /* + * Return failure if msi-map exist and no entry for RID because dwc common + * driver will skip setting up built-in MSI controller if msi-map existed. + * + * err_m target + * 0 NULL Return failure, function not work. + * !0 NULL msi-map not exist, use built-in MSI. + * 0 !NULL Find one entry. + * !0 !NULL Invalidate case. + */ + if (!err_m && !target) + return -EINVAL; + else if (target) + of_node_put(target); /* Find entry for RID in msi-map */ + + /* + * msi-map iommu-map + * Y Y ITS + SMMU, require the same sid + * Y N ITS + * N Y DWC MSI Ctrl + SMMU + * N N DWC MSI Ctrl + */ + if (!err_i && !err_m) + if ((sid_i & IMX95_SID_MASK) != (sid_m & IMX95_SID_MASK)) { + dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); + return -EINVAL; + } + + /* + * Both iommu-map and msi-map not exist, use dwc built-in MSI + * controller, do nothing here. + */ + if (err_i && err_m) + return 0; + + if (!err_i) + return imx_pcie_add_lut(imx_pcie, rid, sid_i); + else if (!err_m) + /* + * Hardware auto add 2 bits controller id ahead of stream ID, + * so mask this 2bits to get stream ID. + */ + return imx_pcie_add_lut(imx_pcie, rid, sid_m & IMX95_SID_MASK); + + return 0; +} + +static void imx_pcie_disable_device(struct pci_host_bridge *bridge, struct pci_dev *pdev) +{ + struct imx_pcie *imx_pcie; + + imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); + imx_pcie_remove_lut(imx_pcie, pci_dev_id(pdev)); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -941,6 +1109,11 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) } } + if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { + pp->bridge->enable_device = imx_pcie_enable_device; + pp->bridge->disable_device = imx_pcie_disable_device; + } + imx_pcie_assert_core_reset(imx_pcie); if (imx_pcie->drvdata->init_phy) @@ -1292,6 +1465,8 @@ static int imx_pcie_probe(struct platform_device *pdev) imx_pcie->pci = pci; imx_pcie->drvdata = of_device_get_match_data(dev); + mutex_init(&imx_pcie->lock); + /* Find the PHY if one is defined, only imx7d uses it */ np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); if (np) { @@ -1587,7 +1762,8 @@ static const struct imx_pcie_drvdata drvdata[] = { }, [IMX95] = { .variant = IMX95, - .flags = IMX_PCIE_FLAG_HAS_SERDES, + .flags = IMX_PCIE_FLAG_HAS_SERDES | + IMX_PCIE_FLAG_HAS_LUT, .clk_names = imx8mq_clks, .clks_cnt = ARRAY_SIZE(imx8mq_clks), .ltssm_off = IMX95_PE0_GEN_CTRL_3,