[v5,14/27] sfc: create type2 cxl memdev

Message ID	20241118164434.7551-15-alejandro.lucero-palau@amd.com (mailing list archive)
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Headers	show Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2046.outbound.protection.outlook.com [40.107.100.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3E0A1C2432; Mon, 18 Nov 2024 16:45:09 +0000 (UTC) Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.12 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.12; helo=SATLEXMB03.amd.com; pr=C From: <alejandro.lucero-palau@amd.com> To: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>, <dan.j.williams@intel.com>, <martin.habets@xilinx.com>, <edward.cree@amd.com>, <davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>, <edumazet@google.com> CC: Alejandro Lucero <alucerop@amd.com> Subject: [PATCH v5 14/27] sfc: create type2 cxl memdev Date: Mon, 18 Nov 2024 16:44:21 +0000 Message-ID: <20241118164434.7551-15-alejandro.lucero-palau@amd.com> In-Reply-To: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain
Series	cxl: add type2 device basic support \| expand [v5,00/27] cxl: add type2 device basic support [v5,01/27] cxl: add type2 device basic support [v5,02/27] sfc: add cxl support using new CXL API [v5,03/27] cxl: add capabilities field to cxl_dev_state and cxl_port [v5,04/27] cxl/pci: add check for validating capabilities [v5,05/27] cxl: move pci generic code [v5,06/27] cxl: add function for type2 cxl regs setup [v5,07/27] sfc: use cxl api for regs setup and checking [v5,08/27] cxl: add functions for resource request/release by a driver [v5,09/27] sfc: request cxl ram resource [v5,10/27] cxl: harden resource_contains checks to handle zero size resources [v5,11/27] cxl: add function for setting media ready by a driver [v5,12/27] sfc: set cxl media ready [v5,13/27] cxl: prepare memdev creation for type2 [v5,14/27] sfc: create type2 cxl memdev [v5,15/27] cxl: define a driver interface for HPA free space enumeration [v5,16/27] sfc: obtain root decoder with enough HPA free space [v5,17/27] cxl: define a driver interface for DPA allocation [v5,18/27] sfc: get endpoint decoder [v5,19/27] cxl: make region type based on endpoint type [v5,20/27] cxl/region: factor out interleave ways setup [v5,21/27] cxl/region: factor out interleave granularity setup [v5,22/27] cxl: allow region creation by type2 drivers [v5,23/27] sfc: create cxl region [v5,24/27] cxl: add region flag for precluding a device memory to be used for dax [v5,25/27] sfc: specify avoid dax when cxl region is created [v5,26/27] cxl: add function for obtaining params from a region [v5,27/27] sfc: support pio mapping based on cxl

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CC: Alejandro Lucero <alucerop@amd.com>
Subject: [PATCH v5 14/27] sfc: create type2 cxl memdev
Date: Mon, 18 Nov 2024 16:44:21 +0000
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Series

cxl: add type2 device basic support | expand

Commit Message

Lucero Palau, Alejandro Nov. 18, 2024, 4:44 p.m. UTC

From: Alejandro Lucero <alucerop@amd.com>

Use cxl API for creating a cxl memory device using the type2
cxl_dev_state struct.

Signed-off-by: Alejandro Lucero <alucerop@amd.com>
---
 drivers/net/ethernet/sfc/efx_cxl.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c
index 9f862fc5ebfa..7e900fbbc28e 100644
--- a/drivers/net/ethernet/sfc/efx_cxl.c
+++ b/drivers/net/ethernet/sfc/efx_cxl.c
@@ -95,10 +95,19 @@  int efx_cxl_init(struct efx_probe_data *probe_data)
 	 */
 	cxl_set_media_ready(cxl->cxlds);
 
+	cxl->cxlmd = devm_cxl_add_memdev(&pci_dev->dev, cxl->cxlds);
+	if (IS_ERR(cxl->cxlmd)) {
+		pci_err(pci_dev, "CXL accel memdev creation failed");
+		rc = PTR_ERR(cxl->cxlmd);
+		goto err3;
+	}
+
 	probe_data->cxl = cxl;
 
 	return 0;
 
+err3:
+	cxl_release_resource(cxl->cxlds, CXL_RES_RAM);
 err2:
 	kfree(cxl->cxlds);
 err1: