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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.12 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.12; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.12) by DS2PEPF00003447.mail.protection.outlook.com (10.167.17.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8158.14 via Frontend Transport; Mon, 18 Nov 2024 16:44:50 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 18 Nov 2024 10:44:49 -0600 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 18 Nov 2024 10:44:48 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v5 04/27] cxl/pci: add check for validating capabilities Date: Mon, 18 Nov 2024 16:44:11 +0000 Message-ID: <20241118164434.7551-5-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB04.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003447:EE_|CH0PR12MB8532:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f70ad99-3ff7-4897-ef17-08dd07f051f1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: i52Jy4ieD8m73coEaCUkT0Wn9mpSBXugNgenZQJHUW5JydQZ1vo6TngNIqRvmTY0jK8XRIa2YzzRxpezpGNGmEjgY6+bu/fp0GS2rU7N/ty1+T77YEtQcnPxyziDH1lUqZRup35tobgiSqQszZeoF0kMxpGBmuZu/Qhv2msmSwu600yLoRT2HdV1jfNDzDgRf6hl0Ie6/H1ok9zeCSnf9ncjrlWoml7c1RI5LNSjruaJbvHwcbHNZ3dn/qr+KCkJU10Y7oKVmcNeAwJjorfUUtlZ/m/oaz08tP1FIouzB3vKqz41+RFED3UdelxDbXvk8NzDuqGhZB2V/SoTdYEMt26XEVhB6OzL/XR08b4yrWs8dDAwd8gSONF2PJM/Coo4xXlsp98WCEDGmO2C5oXON59pAoSF7g20DfwOqYgFsarEkCd7danAzcgZJjte3g6ez05fLrXXJIKyuoMGPL6TyAq2Gn7T4lWaGbWJijbzZlFxTyPerqioR5Y3TICK1jUqFmiC4M62wzfvR4DqJbTufEpclVlHq4UVOLSpXKyYUKAlMwgHuGbpVUhLljNy2YGuKDM8D24MDTH/WAtZTjWMogIPHYwX3vKGhIs9CWOuYl/aXiPAkDDyHC4ri0dAYL+2RLtH/i5Dmbp41RqSx4+yqrvRUjikXeqqPOcshcQINJNpTLFedWtXJptHcozCrY2N/J1qp35+/hR3v6i3POBtDHWF2D4jNHgvpyprrOy0m1dS8CkiKF5ynUjfK6T2C6Jm7PYNtr6KNyiy1oNaI2vOky2jtOvqDXHVAeY2LL+Cb+rXTSn890Fx/wFYaQjwgXB8CNggW/ztvRpQRy/FxhFlQeI6CLEZFaskj7KzB8O2aXbIgGY9w2WkhKkez4pL2nXpVF3wt6S/sUQwggqCrZQMPqoJJkLYUiD6r6ybx03Mi07edTkYiXrwtN5qIKhNcEpnI8prwbUqQQRFcb0Loq9od1VmyNPZCmLjh3yejPuknrDULPTblREyOQy3rSYaHYy8T6ZqeClvzqW7CLpEVAvwhKAl81OFFNbLHrjjrxquU7HnRa6M7V/8S02XFCn+LncY6Fbbp2Y1ZWlN61mirTol2t+F+RdDW+7eJRQ5NsX0xiS6QwmHZ02rKKF5dZBWUruMNRqDp9aQwL/GvF9zq+9kjBR8zquKphqPAoEgG7VivEIUFBbWe5xha62dde5OdohRpuN2xRTF7jhczEuDHj/fvZVCRL6bHUj5wkW1Z4JoE4zzTlYE9mFSdNu5dnCX6X7nBF3SHTgCtdcv/Hm+5g3bNgc0k5ZtkRgO7sOfT3LzKO+ijg87phGJ2zIYfGBWnSfkc+xry37EfxDb2WlQ1orVaLOQ0776EtT2WCcrc0Hc3NhosX/+Iv3m1x418jBA4+2V/Qkmp21suh7mT/hXri44wQ== X-Forefront-Antispam-Report: CIP:165.204.84.12;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:atlvpn-bp.amd.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 16:44:50.3740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f70ad99-3ff7-4897-ef17-08dd07f051f1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003447.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB8532 From: Alejandro Lucero During CXL device initialization supported capabilities by the device are discovered. Type3 and Type2 devices have different mandatory capabilities and a Type2 expects a specific set including optional capabilities. Add a function for checking expected capabilities against those found during initialization. Allow those mandatory/expected capabilities to be a subset of the capabilities found. Rely on this function for validating capabilities instead of when CXL regs are probed. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 22 ++++++++++++++++++++++ drivers/cxl/core/regs.c | 9 --------- drivers/cxl/pci.c | 24 ++++++++++++++++++++++++ include/cxl/cxl.h | 6 +++++- 4 files changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index ff266e91ea71..a1942b7be0bc 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1055,3 +1056,24 @@ int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) return 0; } + +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, + unsigned long *current_caps, bool is_subset) +{ + DECLARE_BITMAP(subset, CXL_MAX_CAPS); + + if (current_caps) + bitmap_copy(current_caps, cxlds->capabilities, CXL_MAX_CAPS); + + dev_dbg(cxlds->dev, "Checking cxlds caps 0x%08lx vs expected caps 0x%08lx\n", + *cxlds->capabilities, *expected_caps); + + /* Checking a minimum of mandatory capabilities? */ + if (is_subset) { + bitmap_and(subset, cxlds->capabilities, expected_caps, CXL_MAX_CAPS); + return bitmap_equal(subset, expected_caps, CXL_MAX_CAPS); + } else { + return bitmap_equal(cxlds->capabilities, expected_caps, CXL_MAX_CAPS); + } +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, CXL); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 8287ec45b018..3b3965706414 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -444,15 +444,6 @@ static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map, caps); - if (!dev_map->status.valid || !dev_map->mbox.valid || - !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", - !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", - !dev_map->memdev.valid ? "memdev " : ""); - return -ENXIO; - } - dev_dbg(host, "Probing device registers...\n"); break; default: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 528d4ca79fd1..5de1473a79da 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -813,6 +813,8 @@ static int cxl_pci_type3_init_mailbox(struct cxl_dev_state *cxlds) static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct cxl_memdev_state *mds; struct cxl_dev_state *cxlds; struct cxl_register_map map; @@ -874,6 +876,28 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + bitmap_clear(expected, 0, CXL_MAX_CAPS); + + /* + * These are the mandatory capabilities for a Type3 device. + * Only checking capabilities used by current Linux drivers. + */ + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_DEV_STATUS, 1); + bitmap_set(expected, CXL_DEV_CAP_MAILBOX_PRIMARY, 1); + bitmap_set(expected, CXL_DEV_CAP_DEV_STATUS, 1); + + /* + * Checking mandatory caps are there as, at least, a subset of those + * found. + */ + if (!cxl_pci_check_caps(cxlds, expected, found, true)) { + dev_err(&pdev->dev, + "Expected mandatory capabilities not found: (%08lx - %08lx)\n", + *expected, *found); + return -ENXIO; + } + rc = cxl_pci_type3_init_mailbox(cxlds); if (rc) return rc; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index dcc9ec8a0aec..ab243ab8024f 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -39,7 +39,7 @@ enum cxl_dev_cap { CXL_DEV_CAP_DEV_STATUS, CXL_DEV_CAP_MAILBOX_PRIMARY, CXL_DEV_CAP_MEMDEV, - CXL_MAX_CAPS = 32 + CXL_MAX_CAPS = 64 }; struct cxl_dev_state *cxl_accel_state_create(struct device *dev); @@ -48,4 +48,8 @@ void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec); void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial); int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, + unsigned long *expected_caps, + unsigned long *current_caps, + bool is_subset); #endif