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Mon, 18 Nov 2024 10:44:51 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v5 06/27] cxl: add function for type2 cxl regs setup Date: Mon, 18 Nov 2024 16:44:13 +0000 Message-ID: <20241118164434.7551-7-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003443:EE_|DS0PR12MB8561:EE_ X-MS-Office365-Filtering-Correlation-Id: 6789d755-b044-4b91-06a1-08dd07f053c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: 1YEeX4VLtrnGZWgBOdCAQVWG1out3ctdc2YDRwL1RjLLfNiTt91TCthfuUMvfA3sqeesyv2tsN9cDSRGsX1YMOsZggSMjWt65st02B0ZtwHRJ7VVaPSwqXSualPzxNGvh29Q/wIq3R3rk2KiE861psYJTLz9DdhRk1ycUXiSZ5MZTOoBMyCTGLuTWF1DaeSMOf5Tn5JSLkRfZi1ho+LFifbvGuIIVBfJPWH39pFqPfhBZzeH1CTQk1VcWT9iyhcE4jwX5pI1Q13l7nUaNLKxr6ZUmj8psdRJvnViJg4RJoGdmGqPfLyvL5gjbGNbDOU50cfFPmeHI1PpKUVAhr+zEmLaHrfpqpGzlGq0Ltxx0Q8pIYrqTEssp7vKfgn29re9NBDvcjNoqnQ1HEjhUQ5UZmLWDwVFaKRJ35qGLOQ6uQDf/o6l9SOxU3pybQ63YaoJpBLWMNoMarmbqODlHngEeZiqp6zqmu0y2RltT8PhczURpE9wu2l938x271Q/zRVcNlxjFBMHKzdETRGXBymsdIcaqZXCCGS37Ik5oFfK+pkj+BrE88w1iWM/uuZAnjGa+1n0KUZk7v2YUKy9wzD+dRQjkTovXaEjd2m18+fI4tBwjCzECXyGRtFreP5vSEwNW1Tp7xjknmRYZ3NOIY4xLBTFRbjGNf8VrrSxG7rfv1A5dsAOQlE4v5vWCNl1PCd59QHNB1wY/0VAFmOZogLbL3EaAJ4wHLIzWqtLNzPoOylIKEUQoZd3dIm3iNQGWUW0HHHNBzzER3/ots7w6Vc6lSjXYCfUUS8PEHFZH28pDBlyxikobxzWcx5JnI3VNBsxJ5lBNov6Fx1A8YQPq8Ak8iujjzq3NeQVEob5qzGGxLYehd7PU1FNtoWAqhSmp0z8D12ycX19w/2JVWbpdKIuFnOmc3Wifv4v3i9IowYII2JSoxBUoyiFopNM6p140kJMGz5YDkgB+plNzqeuqRAqraku+PkOvxxSsghdicJq/Slcxuh5F9RYPJsV1dG2OHnz/LXvYfQA4Hz6H+mKEQWWPT/FL2SqcQqfOv4qNeapN+NeGqVHqJwsmuMMkf74Up+jvUsL7UiYAAdOwbSiPqgjHY92H6Mz8aSyBwYDmMa9Nx8brj1JsL/2dDKtdYZcQKJmJTWl9oe3ZhMz6iEsaT8F+5c4jCAMi5owfl0+w7c2jvcambOqcugeY+9tSsjkQqiNuhuXEZknM9gEJAwTJ0nYpHivoyHmboluueV3q9qgDSFtu1/nDOx7jdMHXEMQKGV27dOD3LymDMc1UCmuamVg6OHbKZprfvJ/njx1w/LBD/SfpTFkkcpgtEStKQSOlTRNv7WtOj7hOHCgRlmLSDLcx3GjXiqE73BKKlyXiKIUMaOoPWk6VEAo9s+q6NjZ1aM/ugZ622VzAztz+ifSgDePTg== X-Forefront-Antispam-Report: CIP:165.204.84.12;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:atlvpn-bp.amd.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 16:44:53.4663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6789d755-b044-4b91-06a1-08dd07f053c5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003443.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8561 From: Alejandro Lucero Create a new function for a type2 device initialising cxl_dev_state struct regarding cxl regs setup and mapping. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 47 ++++++++++++++++++++++++++++++++++++++++++ include/cxl/cxl.h | 2 ++ 2 files changed, 49 insertions(+) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index bfc5e96e3cb9..8b9aa2c578e1 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1096,6 +1096,53 @@ int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); +static int cxl_pci_setup_memdev_regs(struct pci_dev *pdev, + struct cxl_dev_state *cxlds) +{ + struct cxl_register_map map; + int rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, + cxlds->capabilities); + /* + * This call returning a non-zero value is not considered an error since + * these regs are not mandatory for Type2. If they do exist then mapping + * them should not fail. + */ + if (rc) + return 0; + + return cxl_map_device_regs(&map, &cxlds->regs.device_regs); +} + +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) +{ + int rc; + + rc = cxl_pci_setup_memdev_regs(pdev, cxlds); + if (rc) + return rc; + + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->reg_map, cxlds->capabilities); + if (rc) { + dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + return rc; + } + + if (!test_bit(CXL_CM_CAP_CAP_ID_RAS, cxlds->capabilities)) + return rc; + + rc = cxl_map_component_regs(&cxlds->reg_map, + &cxlds->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS)); + if (rc) + dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + + return rc; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_accel_setup_regs, CXL); + int cxl_pci_get_bandwidth(struct pci_dev *pdev, struct access_coordinate *c) { int speed, bw; diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index ab243ab8024f..a88d3475e551 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -5,6 +5,7 @@ #define __CXL_H #include +#include enum cxl_resource { CXL_RES_DPA, @@ -52,4 +53,5 @@ bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, unsigned long *current_caps, bool is_subset); +int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds); #endif