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Mon, 18 Nov 2024 10:44:53 -0600 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Mon, 18 Nov 2024 10:44:52 -0600 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v5 07/27] sfc: use cxl api for regs setup and checking Date: Mon, 18 Nov 2024 16:44:14 +0000 Message-ID: <20241118164434.7551-8-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> References: <20241118164434.7551-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|PH0PR12MB7840:EE_ X-MS-Office365-Filtering-Correlation-Id: db6165fa-e798-456e-c4c2-08dd07f057e4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2024 16:45:00.4009 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db6165fa-e798-456e-c4c2-08dd07f057e4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.12];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7840 X-Patchwork-Delegate: kuba@kernel.org From: Alejandro Lucero Use cxl code for registers discovery and mapping. Validate capabilities found based on those registers against expected capabilities. Signed-off-by: Alejandro Lucero --- drivers/net/ethernet/sfc/efx_cxl.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 99f396028639..d6afd1b5499f 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -21,6 +21,8 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct pci_dev *pci_dev; struct efx_cxl *cxl; struct resource res; @@ -65,6 +67,23 @@ int efx_cxl_init(struct efx_probe_data *probe_data) goto err2; } + rc = cxl_pci_accel_setup_regs(pci_dev, cxl->cxlds); + if (rc) { + pci_err(pci_dev, "CXL accel setup regs failed"); + goto err2; + } + + bitmap_clear(expected, 0, CXL_MAX_CAPS); + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_RAS, 1); + + if (!cxl_pci_check_caps(cxl->cxlds, expected, found, false)) { + pci_err(pci_dev, + "CXL device capabilities found(%08lx) not as expected(%08lx)", + *found, *expected); + goto err2; + } + probe_data->cxl = cxl; return 0;