| Message ID | 20241125-v6-12-topic-socfpga-agilex5-v2-1-864256ecc7b2@pengutronix.de (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | ARM64: dts: intel: agilex5: add nodes and new board | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Not a local patch |
On 25/11/2024 11:33, Steffen Trumtrar wrote: > gpio0 is the same as gpio1 with a different base address. > > Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> > --- Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 1162978329c1637aa0fd9a4adef16a9ae5017ac3..b1debf0317d0576f7b00200e9593481671183faa 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -222,6 +222,25 @@ i3c1: i3c@10da1000 { status = "disabled"; }; + gpio0: gpio@10c03200 { + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03200 0x100>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&rst GPIO0_RESET>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + gpio1: gpio@10c03300 { compatible = "snps,dw-apb-gpio"; reg = <0x10c03300 0x100>;
gpio0 is the same as gpio1 with a different base address. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)