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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , Carolina Jubran , "Cosmin Ratiu" , Tariq Toukan Subject: [PATCH mlx5-next V4 03/11] net/mlx5: Add support for new scheduling elements Date: Tue, 3 Dec 2024 22:29:16 +0200 Message-ID: <20241203202924.228440-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241203202924.228440-1-tariqt@nvidia.com> References: <20241203202924.228440-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006002:EE_|CH2PR12MB9494:EE_ X-MS-Office365-Filtering-Correlation-Id: 0db7c381-6019-4d07-6ba2-08dd13d954f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: suQnd/oT4WcpAu8A6xGshohr9NLe5pXzc0GkWkFqRy/m65l6pjaIVot7VotHfWKtAaauUn2kXTPbvtZa7BWnWiIq9abrG12VLTwNxRZNgJfkWP5uv50b65Mwed1UsXmCOeeeRy83XbhAi8Spjw2mBW4LJT05IwmNgduc11/69rvj8xOJ9HlQLiNBJWTc89vmdBnInvVlVU2v9aWtbm9D4kn/rHnqSHzeXMzMK1l8Hh0SB/r0CnoMC2OjNjHGNOkJEahAa7yTSZ3f9Ig09E91WaW891LMG9K5pGcPrgQ/d7vnAPGVaH54W6wwwcodELaE3rmBLZUHi+Mj1dj9CUzgZz5QwHhzU+9x0TaJ/23W8I41gQl0OAGaeRNjI7YntwfIZSF/fHtCchYL2QuNovOd5ftxuqhzeyJ3JFP4LF4MUuwNgdkRxXQp58ZpnUWiL7mXeJdBGDN0IFYK9QSEXzKfwZTlP5uPSA9UUoMiKy8yD41kqtz09uNyUHZPoqHixrWyk06gVXhTjch2/YVzmM8XASeyDsnw7hQuu5TML2dPggVjJc/fPu36R+eG07o9v1Eo7eR4yaKmNL9Rk5ynDGA7aECTAHLIkmywkHZvJsEIdjt2KOyONr5PaNQDx6qM4JXlcVuqmEAxm2PaHFWvTKxkKg5LAcN4z/QLuyFg2xNjy7mgCgK5rsbrmENQ+Ah6E5JwX+4vZIf+cICn21bPYlxrLS3KghCs10MGgRBgIg2lJPDuDI60jTT6gzqQf5+xeej3vTSVAT5OTcD0g2ZucylM8KVAnjpED6Hz+8e0ajUAvtI09hXTR/L+yCvJGMN2AiAj2zAXfG6vWi02p09+ff4v16uKt5tgpohdUo+XRdhMvSIHWyTDRWsTXZ/UdqzHdo2hypxolxPd/FFd9nLtJ2P5htjJesdbSSgw8/bOmiJgK63KI+qDq2th5YhIjgv8jGVf3kDohs+TefoAeCf6p6uF8ZOybiU0GJm01ljPS2t/T6fP4fPB2bkpvvYnyMK8ozRFKg8hlRABcBwyaOKuXoLDPAq4vtKH1M4OIPoio5vSGN1AdmotW5SjMRyhlNSIKLtWIpZc4Ti0Q2IEYlDRVb9jE9EVENIs+StdtRQfytkcnI5UhoRtW7Qnue1c1a1DWBXumciNPJ/kyUX9LkaC8YMuOR8qirSoV5B9kRwUV6Yt+m0Muo0rPetQvNzl1KlrQ/J3eu4w3whFaiBpiTN9FHKWUtthznW2AdkJB/XuRYYOoOCvaH1x4HtRWIavNPETjpgpjcOwmmKQBic4FxpgeiBgtRZSJ8qUf9/xNTt8/GpWsSICePS1+l0TcIaPg05QLUoyJBfzfDYGTLxIV6a+/P1mmHXVZN9yfaMasCmofvtSJ0DPcCJU+ju9lXwy5OXOb3QMMRX3MoY7be9ytqPFxCUXNDV4EM37d/g7ZYjt2MNzBdY71v/wLYMLNRi0RllymomA X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2024 20:30:30.8935 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0db7c381-6019-4d07-6ba2-08dd13d954f7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006002.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9494 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce new scheduling elements in the E-Switch QoS hierarchy to enhance traffic management capabilities. This patch adds support for: - Rate Limit scheduling elements: Enables bandwidth limitation across multiple nodes without a shared ancestor, providing a mechanism for more granular control of bandwidth allocation. - Traffic Class Transmit Scheduling Arbiter (TSAR): Introduces the infrastructure for creating Traffic Class TSARs, allowing hierarchical arbitration based on traffic classes. - Traffic Class Arbiter TSAR: Adds support for a TSAR capable of managing arbitration between multiple traffic classes, enabling improved bandwidth prioritization and traffic management. No functional changes are introduced in this patch. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/rl.c | 4 ++++ include/linux/mlx5/mlx5_ifc.h | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index e393391966e0..39a209b9b684 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c @@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN; case TSAR_ELEMENT_TSAR_TYPE_ETS: return cap & TSAR_TYPE_CAP_MASK_ETS; + case TSAR_ELEMENT_TSAR_TYPE_TC_ARB: + return cap & TSAR_TYPE_CAP_MASK_TC_ARB; } return false; @@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC; case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP: return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP; + case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT: + return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT; } return false; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index bd9b1833408e..8b202521b774 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1103,7 +1103,8 @@ struct mlx5_ifc_qos_cap_bits { u8 packet_pacing_min_rate[0x20]; - u8 reserved_at_80[0x10]; + u8 reserved_at_80[0xb]; + u8 log_esw_max_rate_limit[0x5]; u8 packet_pacing_rate_table_size[0x10]; u8 esw_element_type[0x10]; @@ -4104,6 +4105,7 @@ enum { SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, + SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, }; enum { @@ -4112,22 +4114,26 @@ enum { ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, + ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, }; enum { TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, + TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, }; enum { TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, TSAR_TYPE_CAP_MASK_ETS = 1 << 2, + TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, }; struct mlx5_ifc_tsar_element_bits { - u8 reserved_at_0[0x8]; + u8 traffic_class[0x4]; + u8 reserved_at_4[0x4]; u8 tsar_type[0x8]; u8 reserved_at_10[0x10]; }; @@ -4164,7 +4170,9 @@ struct mlx5_ifc_scheduling_context_bits { u8 max_average_bw[0x20]; - u8 reserved_at_e0[0x120]; + u8 max_bw_obj_id[0x20]; + + u8 reserved_at_100[0x100]; }; struct mlx5_ifc_rqtc_bits {