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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" CC: , Saeed Mahameed , Gal Pressman , Leon Romanovsky , , Cosmin Ratiu , Tariq Toukan Subject: [PATCH net-next V4 04/11] net/mlx5: qos: Add ifc support for cross-esw scheduling Date: Tue, 3 Dec 2024 22:29:17 +0200 Message-ID: <20241203202924.228440-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241203202924.228440-1-tariqt@nvidia.com> References: <20241203202924.228440-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003448:EE_|BY5PR12MB4146:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d98d4ec-1c84-4ae5-7a2f-08dd13d95534 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: Rrynmgh3pfMPfEZUKJoSU7JUu6u6pKRfHr/vXuBTyCTkDgINpy2/z462ykFqYw3e3p71w+1LJ1fxehreSvfI+SLldk/tZs1Y/OA3rTjJ8AJ6B2n40HWME9i6hTGL4rkXQE+XCi7NrzkS7J4ymqLAojPjuZFGpDcQNQBWkktMFE0vOgT80HC1lbSIqthBQHcFzPj3Ly0+NMIBIpcav+iAB1GlfdgunmB9z+d3gVm1AJkT/fsxP7Y+Hl2caOUTH3UCnGBQkqCvHXfEPW8impxIpZLcz0H7AAt7IH3XnKJPtxhECQbVqFASXkEcPCJgoxqtdbkqPnVMSetnpew4lNPGPAK+DIkksVs1cF6+P/2+J1JJLD8XZuzcbE711TwGTX5E57cVO9yTbIN4x5z8YsTWPjo3qOvPTqxH3h6fY6cYjelf2JwTzmC2bsMxFACcudRDNvvgsN4yJeGu0BVsqNUe0pCRk8BOHvr78lwW9UTCv27QvMT1guQEwU/7giv6W1BQuGAvf+jPzpnPWVrwIsvWWFEB5tOAONpYqKyQvS4VDZDyTYsTXkYaDuTTQfIF5urb58xcXqil8VDJihyNlNFbsareGcEwAOYk4jByxCRTcA5GuFiZlDAcwJI3xnVJip3lXWY+FZoWq1PxZ4zzHEdoxSjnRkud4P6o/HZUaCbcH3nDY6BdfG36j697mn1chuOqfAObKwu0nBkBOUquM7Gf4bPWGzoXG6OfXFTS/iBs68nEGQdSdDkLvO01PyrE6Ih+rg2XtUpwMT0Y4Y6sxRD3reNrBnFS6yIX65+BIQbrf4StlitaiVp8DQCAHElrggh/NPxXHUJJlVhSGXz12hw6S0XDyvDwrBtAuW2LtD99ew177EpWCQ1/RSjsMy/rooPjGkvb4V9vAzGfWkTLOwDpcTqsBMpxR/LJ8fVCjPz/iU95W4CJMAjo1FBp3QCJEYZkQ5++HlUs7ImCRX4Dn6gGdm5PUJhbsCeQwQICgr4dcV5gpz+Q+YkiVL7n8QSg6ZGTcIJesHYn0hKoTFtwat9Mwpn9AIHvxRDNmq6m1TxK6ONo1+IrvzoeM1cUSUSrD9tndUXrcaH/zpd9xijdHQZ/EMacjnFJlDasFuD8jPclRt5fACc9Fjuyqd8OiKOsawh8sVYCGNVciZ6TSlhQh4OejeYqK4XazeNbsmQruJRKT3IWgYz7ekF7gtSt9W7LGAT8Y3zAMTHp0J9vQu3qvzLQJLxz3Q0tkmV99NVGijwvmmEmXW4pSP28ymZX2yQ+AMC6Ayu+h45345WB6YCvg5llZl6Aq5Pn3DObu5+QfSitq1accYX7B6yY2X+15B+d2AQBqwBOqZE8C2wnE7FmKinUZSMZvQwsRP3HJDAB1dqJuYKfZI9Kx9Dx4XC0otErx+hdyW2YxD30hIU1XI16vXOeEUQTq5/xuTXleqZN/zYxpvW9V50fCjF154ddeCzWX7xz X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Dec 2024 20:30:31.3561 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d98d4ec-1c84-4ae5-7a2f-08dd13d95534 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003448.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4146 X-Patchwork-Delegate: kuba@kernel.org From: Cosmin Ratiu This adds the capability bit and the vport element fields related to cross-esw scheduling. Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 8b202521b774..5451ff1d4356 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1095,7 +1095,9 @@ struct mlx5_ifc_qos_cap_bits { u8 log_esw_max_sched_depth[0x4]; u8 reserved_at_10[0x10]; - u8 reserved_at_20[0xb]; + u8 reserved_at_20[0x9]; + u8 esw_cross_esw_sched[0x1]; + u8 reserved_at_2a[0x1]; u8 log_max_qos_nic_queue_group[0x5]; u8 reserved_at_30[0x10]; @@ -4139,13 +4141,16 @@ struct mlx5_ifc_tsar_element_bits { }; struct mlx5_ifc_vport_element_bits { - u8 reserved_at_0[0x10]; + u8 reserved_at_0[0x4]; + u8 eswitch_owner_vhca_id_valid[0x1]; + u8 eswitch_owner_vhca_id[0xb]; u8 vport_number[0x10]; }; struct mlx5_ifc_vport_tc_element_bits { u8 traffic_class[0x4]; - u8 reserved_at_4[0xc]; + u8 eswitch_owner_vhca_id_valid[0x1]; + u8 eswitch_owner_vhca_id[0xb]; u8 vport_number[0x10]; };