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Wed, 4 Dec 2024 14:11:07 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Leon Romanovsky CC: , Saeed Mahameed , Gal Pressman , , Cosmin Ratiu , Tariq Toukan Subject: [PATCH mlx5-next V5 01/11] net/mlx5: ifc: Reorganize mlx5_ifc_flow_table_context_bits Date: Thu, 5 Dec 2024 00:09:21 +0200 Message-ID: <20241204220931.254964-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241204220931.254964-1-tariqt@nvidia.com> References: <20241204220931.254964-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00029927:EE_|CY8PR12MB8265:EE_ X-MS-Office365-Filtering-Correlation-Id: e6e373ce-5fc3-40ff-097a-08dd14b09d70 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: NvI8shlXm+0U1hnqt7zjuCXleL0Yk5fJ57glGj1b7KpiM2cPIK+s9svbgoCmQQPw9C1lBfqViYgDi1pnB4Bcyexn+MVaesByrrk6cLLqtDXsFO5XmDumUUrf43IughgoLsxn0FW3zPkbD1Z9hFurPlfNKQJhQwfS1gl0alguyfKxsALYQAvF7HDSZ20iCK6GRlAlCM/oP+rx+Lel61Q+mWTFhcm5ouSlxPpu9NU1RvgzpsWpbNaRpEwJ9PGJy8ppknaWYBq5zK1WIeDl01koPwmfM5XrbM/BnrO4eOGp2Mix0DdC3unNiDg2txE4C7WEZabLlNatZT2m0lXG4rKEOlAyLf1RVwjDHLrl0g1DRusCKCqY5RX8RucvCT03FNgYidA6ACKAmG0VDeP8A8sS0iGza79RUNtYMmmuAongDOcNgMCQ9nK7w0oiJqQZBXOdz/BZgj9lxlNKKwxg/8QsN1I2KJnK3W6ZoxmrpC/Eytonfi/p6OjKM16+yRRjzlkyXDterj3iDL2Xl5tcflSIdcRLYRb3z9VClBBUib/YcpS9nEBcwxukkV2BY5QdwA6XzDPjk73B0h0RN0NwOrOx1HDgl4fp2MEwjaiEVOhbabgJYkYuVsJLXOqQ8niKt/ZrNFEU4khb6M3+pf4xLtQHU1ef1b2gYDIAWLwNeEOcFwjQTipmh/osKzSP04wtmi1ss5GoiP5n7LXch7LEKJ9lHJzYGVUuWhDzg7ktlCoUPYRu/zYHva8d5ZxPniY0jgPrXkd8R/hDBOyC2arkj4Sjv6NgKjBbpcl7bb+23u/F4lXfR4wOnGOUq/vKx0uEx486hlDWoLs1sSIvsz/VhgXuBRlUAGyHtIlPU/WnJRg5mAfnUCMDjk7+Q7Tm4rhH85aR1YhN44lCkkf9rZAdkjc9h8kX547SmvZwsK29rY1wtIMH3tAA91jrvA3egpxIUT/fH2myZgs//VTi0AIblQporp/4P7bUUfyf6QVupvRdrzYFYHsdHqM01RKgZfLSLRnIyCGLU7TUGGrpCzqfhwa6huKz3e5Nel0Z3yS09iJbSuPA4YYneurQQTTT2EEglSHz6omsG16BsFTj2DFRZEPOJ/JqDxoU7TEmjzvh6/r0IaTWfAA3wppeznAb/7wJ7hn1rUBq6Nuy9J+6Cfz+p0/7HjSrFsSEHVWoDjyent2+F/G1w/7n6bSmr6j0AxrRgiE2UdpD7A0FOExbloMtiTT634rRfCxaMQsJ3iTDUxfFldrQ98l3Qbng9F2o/d9rFNYdxG0HEvplkEPRRkJYXVkfSmCVE1sNrIsJVufEvQv0KLXV5eOWEZSIh60SB6WsDZs1/WyWYtEsutu2Wz6SqTkPWJU75P5x0po/Ney+3GvTsKroZwxjUfRw3JhbnjXqOonbRnOY9Ojtn3QIQ1ReSb6O69ntydk7H0ayeWc+gB8vmjTAOZ63MfKYTQtyPMr2heC8 X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2024 22:11:34.2612 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6e373ce-5fc3-40ff-097a-08dd14b09d70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00029927.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8265 From: Cosmin Ratiu The nested union at the end is not in the same style as the rest of the code, so un-nest it to make the style uniformly applied again. Signed-off-by: Cosmin Ratiu Reviewed-by: Saeed Mahameed Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 4fbbcf35498b..f3650f989e68 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -6324,6 +6324,20 @@ struct mlx5_ifc_modify_other_hca_cap_in_bits { struct mlx5_ifc_other_hca_cap_bits other_capability; }; +struct mlx5_ifc_sw_owner_icm_root_params_bits { + u8 sw_owner_icm_root_1[0x40]; + + u8 sw_owner_icm_root_0[0x40]; +}; + +struct mlx5_ifc_rtc_params_bits { + u8 rtc_id_0[0x20]; + + u8 rtc_id_1[0x20]; + + u8 reserved_at_40[0x40]; +}; + struct mlx5_ifc_flow_table_context_bits { u8 reformat_en[0x1]; u8 decap_en[0x1]; @@ -6342,20 +6356,10 @@ struct mlx5_ifc_flow_table_context_bits { u8 lag_master_next_table_id[0x18]; u8 reserved_at_60[0x60]; - union { - struct { - u8 sw_owner_icm_root_1[0x40]; - - u8 sw_owner_icm_root_0[0x40]; - } sws; - struct { - u8 rtc_id_0[0x20]; - u8 rtc_id_1[0x20]; - - u8 reserved_at_100[0x40]; - - } hws; + union { + struct mlx5_ifc_sw_owner_icm_root_params_bits sws; + struct mlx5_ifc_rtc_params_bits hws; }; };