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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Leon Romanovsky CC: , Saeed Mahameed , Gal Pressman , , Carolina Jubran , Cosmin Ratiu , Tariq Toukan Subject: [PATCH mlx5-next V5 03/11] net/mlx5: Add support for new scheduling elements Date: Thu, 5 Dec 2024 00:09:23 +0200 Message-ID: <20241204220931.254964-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241204220931.254964-1-tariqt@nvidia.com> References: <20241204220931.254964-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992C:EE_|DM6PR12MB4044:EE_ X-MS-Office365-Filtering-Correlation-Id: 02a61bba-15c2-4f7c-be63-08dd14b0a0ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: qhw/96JCNVof6QSo47UNE0je1Zodh6iVDzs+odYTpfvN7Pjmun0KPb2YuVkUeimCZpiwI0CzaCqQ4Wc2i3Db5y+wQ2nqXs/eKgY7YqrGOzKNORbkUaxvdDY6j2hMVtxnpveac31UhPaOSMebwBTfzwrvSt3K4pRAt4vzDEkkYBRvtKWPdRQrLFp7nXSumHnarCVxakej2DjBHyXT/6JZvXsfQVAoTxxTakpbKXyrJk45we8fo6XYJ9fArq+rJNyTHulCOPLjHhFcPeg1Cl1zuzKUqRZ/jjyMTLyJOL84xFH1g6iOOece4vrbZ+76tvOnHWpaQvRhFsPCsJqdYNnJHiz9NtmimkoJ+vomLJCdjYOWzXSWivmslfZ+J3kWsk4I4iKdgdcd32EXSoATsWPG2nr8akERcxoDMuYUgUbvDjJqnvXIIIrGpiSqPwychTLCxG30G/U5eU9OSF0gOl3jnI2vev7Virkl4csNQMzXH7mEo0m9k/eSPdcR7ctN29hM080di9q70n6QAT1fOXhDhRDMw9lSheNb1HDd/zjMC3ryYvnz+HsGCYY53DtNABXhoI05ZDoAmjCyfWNQNXn3I+1Jo3aTF4uJ4ttiGUHNJ2SjMc3OJfBFEKfRDaT8E5xalr7XA4DSUtJKPQIDWGrcqckXYuz8FdU07FlNiAQ42wAX/Uj3HnHaiEuO2bzGWlmWSSy7aodqmoJ0ST7y3YVFDmtZNDQsbfQs1wGPwRKMiVlDpEW3N9m88XwXPkj62lvqGzf2zwzjxqu/18QZXi5F7+AMzrTyB86gCRmXyHwEkOnOQ+5xdsWy1Mapc+Rrt/4BgFx7N/ZSUtvlHodgQVt/DVjYtR6JuqMGo89FXIGsaDnLJ4brh8hNPO6z0zmiThWxBzA1CfhuVh9yb8SNz2iypjXp3e/0idm77Vw1eIl09TNy6+KlvH36yvgLpQdWsb+Z85su2Xp07EYJpJADrUaVyM2dyAcjvFefED3XerBhp0H0LnMjzjzthiHan8ELGcEwpJwOm7PgEcQZc76ZcRlHxdv51w8Wd2sxfIY7vAi/IDRs2/gkU4+PACr+JPhS7otDxgFhYbGTPpSkeOrugGcs71YUYU+zLdD0RGkvUGtF8gNGQOnd35ko5UlVFBYmXWV6hRSMqC/P+3zzxPHyKjHsZVZBRHkEE0Z979AQHsXC8HvXKsm7yUqw67ao5MeJgXO4Ijli1p/5yshjuPwKeFFtrQ3fZKa2hH2L0aevy4yLy5SIf94hUdTXri70WNpbj7GSM0NH6fFlfg1/bghj2hSaXZvx8QEPua0exU/ZEf3VgNvhx70wvu4MIhAyMMRMaLnXYr4D9d2nmfGK6h82Q56nS8m2pRadhukDoM3cO7mg+MJO38v8FxGMZMDLowDVesaass1zx8gRY8coPPGDxVIqwVhBVTboPipuV9IdsWe5GD0BOpyTEU1FpetpB9pVfUZI X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2024 22:11:40.0844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 02a61bba-15c2-4f7c-be63-08dd14b0a0ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4044 X-Patchwork-Delegate: kuba@kernel.org From: Carolina Jubran Introduce new scheduling elements in the E-Switch QoS hierarchy to enhance traffic management capabilities. This patch adds support for: - Rate Limit scheduling elements: Enables bandwidth limitation across multiple nodes without a shared ancestor, providing a mechanism for more granular control of bandwidth allocation. - Traffic Class Transmit Scheduling Arbiter (TSAR): Introduces the infrastructure for creating Traffic Class TSARs, allowing hierarchical arbitration based on traffic classes. - Traffic Class Arbiter TSAR: Adds support for a TSAR capable of managing arbitration between multiple traffic classes, enabling improved bandwidth prioritization and traffic management. No functional changes are introduced in this patch. Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/rl.c | 4 ++++ include/linux/mlx5/mlx5_ifc.h | 14 +++++++++++--- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rl.c b/drivers/net/ethernet/mellanox/mlx5/core/rl.c index e393391966e0..39a209b9b684 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c @@ -56,6 +56,8 @@ bool mlx5_qos_tsar_type_supported(struct mlx5_core_dev *dev, int type, u8 hierar return cap & TSAR_TYPE_CAP_MASK_ROUND_ROBIN; case TSAR_ELEMENT_TSAR_TYPE_ETS: return cap & TSAR_TYPE_CAP_MASK_ETS; + case TSAR_ELEMENT_TSAR_TYPE_TC_ARB: + return cap & TSAR_TYPE_CAP_MASK_TC_ARB; } return false; @@ -87,6 +89,8 @@ bool mlx5_qos_element_type_supported(struct mlx5_core_dev *dev, int type, u8 hie return cap & ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC; case SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP: return cap & ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP; + case SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT: + return cap & ELEMENT_TYPE_CAP_MASK_RATE_LIMIT; } return false; diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index bd9b1833408e..8b202521b774 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1103,7 +1103,8 @@ struct mlx5_ifc_qos_cap_bits { u8 packet_pacing_min_rate[0x20]; - u8 reserved_at_80[0x10]; + u8 reserved_at_80[0xb]; + u8 log_esw_max_rate_limit[0x5]; u8 packet_pacing_rate_table_size[0x10]; u8 esw_element_type[0x10]; @@ -4104,6 +4105,7 @@ enum { SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, + SCHEDULING_CONTEXT_ELEMENT_TYPE_RATE_LIMIT = 0x5, }; enum { @@ -4112,22 +4114,26 @@ enum { ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, ELEMENT_TYPE_CAP_MASK_QUEUE_GROUP = 1 << 4, + ELEMENT_TYPE_CAP_MASK_RATE_LIMIT = 1 << 5, }; enum { TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, + TSAR_ELEMENT_TSAR_TYPE_TC_ARB = 0x3, }; enum { TSAR_TYPE_CAP_MASK_DWRR = 1 << 0, TSAR_TYPE_CAP_MASK_ROUND_ROBIN = 1 << 1, TSAR_TYPE_CAP_MASK_ETS = 1 << 2, + TSAR_TYPE_CAP_MASK_TC_ARB = 1 << 3, }; struct mlx5_ifc_tsar_element_bits { - u8 reserved_at_0[0x8]; + u8 traffic_class[0x4]; + u8 reserved_at_4[0x4]; u8 tsar_type[0x8]; u8 reserved_at_10[0x10]; }; @@ -4164,7 +4170,9 @@ struct mlx5_ifc_scheduling_context_bits { u8 max_average_bw[0x20]; - u8 reserved_at_e0[0x120]; + u8 max_bw_obj_id[0x20]; + + u8 reserved_at_100[0x100]; }; struct mlx5_ifc_rqtc_bits {