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Wed, 4 Dec 2024 14:11:18 -0800 From: Tariq Toukan To: "David S. Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , "Andrew Lunn" , Leon Romanovsky CC: , Saeed Mahameed , Gal Pressman , , Cosmin Ratiu , Tariq Toukan Subject: [PATCH mlx5-next V5 04/11] net/mlx5: qos: Add ifc support for cross-esw scheduling Date: Thu, 5 Dec 2024 00:09:24 +0200 Message-ID: <20241204220931.254964-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20241204220931.254964-1-tariqt@nvidia.com> References: <20241204220931.254964-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D3:EE_|PH8PR12MB7255:EE_ X-MS-Office365-Filtering-Correlation-Id: 82eefd5b-a5da-4e2f-70b7-08dd14b09d6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: 8EA44L0Fh/cnEFbIVw0GmHHr1ZJGgXJbfwNmIhNAGEPU1uNJqoRhmcCHCLBFpGjKeTetK18yAurzOS5UJXV4oE6I5m7zw8EPMXhG4Tg1+lFZ6i882CqPCsC2+e86/OCVWrairwth6JNvChjd1kL0iDZj/Ofc7Qmupd4YSkEDcaiFFB9WFCes7E7mrlGjwulhF77YXvJ3ruO0znaWpuFkRoqvHqPk2/uE9Cn6p9I1OaSBsQ9aKPwmjMLtRyncTiuHpEmMCxdbGZQFmXKB3pt+qYHa6phC0VcOVOVM28kVc79UhGQVXMSbJV9xVxiOgOyytScaiSgeWINIWAuMFLeMoUOsAzKE+W2NCR8ESqC2yOZ4VLYqJ8CgK5JClhJVjrjqYa4OTV0By16kdp5D8/ulk6U3ppJjbrsO4rsLzWv+7i/YjhAP3Aw2EVV1isobDeXvwOFjs9bAFOdHkiWbsE52QVq/0GQev/1wA1j9Ju01DpTyGfSDUGxpKeBqy7YekWEOoKhXo8U0jjGUG+I4HTUz3XVsSAwmR9I1D4lAcYeqVThMUGat8KwkRz61sETrUbXFou2R64hAN+pQ5a47bXuEE7+esiqrs1tzG7MXPNBjXCqn0FCW+LuUVQ6pGNAsikdW/cH4TmLwOaYZB5QsR3paVjh37kCxdASjzxKGmdi/KhUcSSl2hOUrQ65iMBU5WqSsnISYxzFui+RqSAIEeR0D2osQB3sVkyv6ML12rw8Izs0hw6Cfyg+pVLBnsHBlnjUlW68SW+ZBlhhxIySVJJHxbAxIIM97PpKe8z5pESkEihSSvDzVRWMhtQap3/k6+CukRAAKCLdLaQEgMSS7coDX9kGZ2go9lS1ffIOGjgSBTHQmuBZdwJtP17JXMRApcs4rDqJkxdbMNTapJe9ZpW2qCrFUAGSuk4VEJoICjz7V5uBW39bO51TiCi39TlsCUbf3aN2/zxRwmQG34HQkAXjwS5NPrx8MVic4RuEeF0raQrp82TwCetLBJAi/vCZJshOqLLayI8b6FjSNCaPNlZvJl5kE+qo3QY152t+QZyYI4Zs97HeHfi8qHmuRmCCG6nvCZUSTpziccqNv/cXrCoenjCixDMub0LE3kRMg8q2zwHi8KYbF8WV3tw82UxMIUUk6cRi5Ju86+Mp1v+KT8+Jyu0iI1gbnhA4wsqfmqWuGdJVtTmmPmgWgIiPm3rFhoj7nfkV97Bs9FWf/0UHNxA4oTBquqiB1rOWVp7YKvDNGxYyp7fRJFH8NNBbMLaZh1kTcAC7Itb8PtfpxpZ7uU5DO6HSH+/gJfg6b/NyYwzO8S7Ytio3gKJIpYtjGFoeCqSoMnZjyTjvikfUBi4+qV3MZqpphnWyUoFIpzEPpOb/rcMkH5j8Z08BeY/cZMgNIfX6WkeZV+g3ebVPsP8UhyXUuSqr6yFfS0fSpgc0OD5eDEXZWEJM9jyN9TeOxi/qzvZPp X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2024 22:11:34.3223 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82eefd5b-a5da-4e2f-70b7-08dd14b09d6d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7255 From: Cosmin Ratiu This adds the capability bit and the vport element fields related to cross-esw scheduling. Signed-off-by: Cosmin Ratiu Signed-off-by: Tariq Toukan --- include/linux/mlx5/mlx5_ifc.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 8b202521b774..5451ff1d4356 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1095,7 +1095,9 @@ struct mlx5_ifc_qos_cap_bits { u8 log_esw_max_sched_depth[0x4]; u8 reserved_at_10[0x10]; - u8 reserved_at_20[0xb]; + u8 reserved_at_20[0x9]; + u8 esw_cross_esw_sched[0x1]; + u8 reserved_at_2a[0x1]; u8 log_max_qos_nic_queue_group[0x5]; u8 reserved_at_30[0x10]; @@ -4139,13 +4141,16 @@ struct mlx5_ifc_tsar_element_bits { }; struct mlx5_ifc_vport_element_bits { - u8 reserved_at_0[0x10]; + u8 reserved_at_0[0x4]; + u8 eswitch_owner_vhca_id_valid[0x1]; + u8 eswitch_owner_vhca_id[0xb]; u8 vport_number[0x10]; }; struct mlx5_ifc_vport_tc_element_bits { u8 traffic_class[0x4]; - u8 reserved_at_4[0xc]; + u8 eswitch_owner_vhca_id_valid[0x1]; + u8 eswitch_owner_vhca_id[0xb]; u8 vport_number[0x10]; };